IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 28

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

28
Symbol
tSCD
tSINT
TrinT
(*) When receiving the first byte in FIFO mode tSINT will be delayed 3 RCLK cycles, except for a
timeout interrupt where tSINT will be delayed 8 RCLK cycles.
Note:
(1)See Read Cycle timing
SAMPLE CLK
Parameter
Delay from RCLK
To Sample Time
Delay from
Stop to Set Interrupt
Delay From IOR*
(RD RBR or RD LSR)
Reset Interrupt
SAMPLE CLK
IOW*(1)
(read LSR)
INTERRUPT
INTERRUPT
(read RBR)
IOR*(1)
LSI
RDR
SIN0
RCLK
START
FIGURE 9 – Receiver Timing
Min
408-432-9100/www.impweb.com
8 CLKS
DATA BITS(5-8)
Max
2
1(*)
32
PARITY
Units
µsec
RCLK Cycles
nsec
STOP
START
ACTIVE
t
t
SCD
RINT
t
t
SINT
SINT
IMP16C552
IMP16C552
ACTIVE
Test Conditions
100pF Load
t
RINT
© 2002 IMP, Inc.