IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 18

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

18
Bit 4, 5: FCR 4 and FCR5 are reserved for
future use.
Bit 6,7: FCR6 and FCR7 are used to set the
trigger level for the RCVR FIFO interrupt as
follows:
MODEM Control Register
This 8-bit register controls the interface with
the MODEM or data set
device emulating a MODEM ). The contents of
the MODEM Control Register are indicated in
Table II and are described below:
Bit 0:
Ready (DTR*) output. When bit 0 is set to a
logic 1, DTR* output is forced to a logic 0.
When bit 0 is reset to a logic 0, DTR* output is
forced to a logic 1.
Note: the DTR* output of the UART may be
applied to an EIA inverting line driver (such
as DS1488) to obtain the proper polarity input
at the succeeding MODEM or data set.
Bit 1: This bit controls the Request to Send
(RTS*) output. Bit 1 affects the RTS* output in
a manner identical to that bit 0 affects output
DTR*.
Bit 2: This bit controls the internal OUTPUT 1
signal, which is an auxiliary user-designated
output. Bit 2 affects the OIUTPUT 1 in a
manner identical to bit 0 affects output DTR*.
Internal OUTPUT1 signal is not connected the
external pin.
Bit 3: This bit controls the internal OUTPUT2
signal, which is an auxiliary user-designated
output. Bit 3 affects the OUT2* output in a
manner identical to bit not connected to the
external pin. When set, this bit enables INT2
pin internally.
Bit 4: This bit provides a local loopback
feature for diagnostic testing of the UART.
7
0
0
1
1
This bit controls the Data Terminal
6
0
1
0
1
RCVR FIFO Trigger
Level (In bytes)
01
04
08
14
(or a peripheral
408-432-9100/www.impweb.com
When bit 4 is set to logic 1, the following occur.
The transmitter Serial Output (SOUT) is set to
a logic 1
Input (SIN) is disconnected; the output of the
Transmitter Shift Register is “looped back” into
the Receiver Shift Register input: the four
MODEM Control inputs (CTS*, DSR*. RLSD*
and RI*) are disconnected. And the MODEM
Control output pins (RST*, DTR*) are forced
to their inactive state (high). In the diagnostic
mode, data that is transmitted is immediately
received. This feature allows the processor to
verify the transmit-and receive-data paths of
the UART.
In the diagnostic mode, the receiver and
transmitter interrupts are full operational. Their
sources are external to the part. The MODEM
control Interrupts are also operational, but the
sources of interrupts are now the lower four
bits of the MODEM Control Register instead of
the four MODEM control inputs. The interrupts
are still controlled by the Interrupt Enable
Register.
Bit 5-7: These bits are permanently set to
logic 0.
MODEM STATUS Register
This 8-bit register provides the current state of
the control lines from the MODEM or data set
(or a peripheral device emulating a modem) to
the CPU. In addition to this current-state
information, four bits of the MODEM Status
Register provide change information. These
bits are set to a logic 1 whenever a control
input from the MODEM changes state. They
are reset to logic 0 whenever the CPU reads
the MODEM Status Register.
The contents of the MODEM Status Register
are indicated in Table II and described below:
Bit 0: This bit is the Delta Clear to Send
(DCTS) indicator. Bit 0 when set to logic 1,
indicates that the CTS* input to the chip has
changed state since the last time it was read
by the CPU.
Bit 1: This bit is the Delta Data Set Ready
(DDSR) indicator, Bit 1 when set to logic 1,
indicates that the DSR input to the chip has
(high) state: the receiver Serial
IMP16C552
IMP16C552
© 2002 IMP, Inc.