IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 10

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

10
INTERALL REGISTER DESCRIPTION
The system programmer has access to any of the register as summerized in Table II
Table II Accessible IMP16c552 Registers for each serial channel
Bit
no
0
1
2
3
4
5
6
7
0DLAB=0
Receiver
Buffer
Register
(Read only)
RBR
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit3
Data Bit4
Data Bit5
Data Bit6
Data Bit7
0DLAB=0
Transmitter
Holding
Register
THR
Data Bit0
Data Bit 1
Data Bit3
Data Bit4
Data Bit5
Data Bit6
Data Bit7
Data Bit 2
1DLAB=0
Interrupt
Enable
Register
IER
Enable
Receiver
Data register
Interrupt
(ERBF)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Enable
Receiver
Line status
(ERLS)
Enable
MODEM
Status
interrupt
(EDSSI)
0
0
0
0
interrupt
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Register address
2
Interrupt
Identification
Register
(Read only)
IIR
``0”if
Interrupt
Pending
Interrupt
ID bit 0
(IIDB0)
Interrupt
ID bit 1
(IIDB1)
Interrupt
ID bit 2
(IIDB2)
0
0
FIFO
Enable(*)
(FE)
FIFO
Enable(*)
(FE)
IMP16C552
IMP16C552
2
FIFO control
Register
(Write only)
FCR
FIFO
Enable
(FEWO)
Receiver
FIFO
Reset
(RFR)
Transmitter
FIFO
Reset
(TFR)
DMA
Mode
Select
(DMS)
Reserved
Reserved
RCVR FIFO
Trigger
Level (LSB)
RCVR FIFO
Trigger
Level (MSB)
3
Line
Control
Register
LCR
Word Length
Select bit 0
(WLSO)
Word
length
Select bit 1
(WLS1)
Number of
Stop Bits
(STB)
Parity
Enable
(PEN)
Even parity
Select (EPS)
Stick parity
(STP)
Set Break
Control
Divisor Latch
Access bit
(DLAB)
© 2002 IMP, Inc.