IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 17

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

17
Bit 6, 7: These two bits, when set, indicate
that the device is in FIFO Mode, i.e. when
FCRO=1.
Interrupt Enable Register
This 8-bit register enables the four interrupt
sources of the DUART to separately activate
the chip Interrupt (INTRPT) output signal.
Each interrupt can individually activate the
interrupt (INTRPT) output signal. Its contents
are indicated in Table 3-2 and are described
below by resetting bits 0 through 3 of the
interrupt Enable Register
setting bits of the IER register to a logic 1
enables the selected interrupt (s). Disabling
an interrupt prevents it from being indicated as
active in the IIR and from activating the
INTRPT output signal. All other system
functions operated in their normal manner,
including the setting of the Line Status and
MODE Status Registers.
Bit 0:
Available Interrupt (and timeout interrupt in
the FIFO mode) when set to logic 1.
Bit 1:
Holding Register Empty Interrupt when set to
logic 1.
Bit 2:
Status Interrupt when set to logic 1.
Bit 3: This bit enables the MODEM Status
Interrupt when set to logic 1.
This bit enables the Received Data
This bit enables the Receiver Line
This bit enables the Transmitter
RCVR Timout Status Interrupt 0/1
RCVR Data Status Interrupt 0/1
RCVR line Status Interrupt 0/1
Internal OUTPUT2(MCR0/1 bit 3)
LOOPBACK enable(MCR0/1 bit
4)
MODEM status interrupt 0/1
FIGURE 3 – Interrupt Control logic for channel 0 and 1
THRE Interrupt 0/1
(IER). Similarly,
408-432-9100/www.impweb.com
Bit 4-7: These four bits are always logic 0.
Scratch Pad Register
This 8-bit Read/Write Register does not
control the UART in anyway. It is intended as
a scratch pad register to be used by the
programmer to hold general purpose data
temporarily.
FIFO Control Register
This write only register is located at the same
address as the IIR (read only). This register
is used to enable FIFO Mode, clear FIFO’s,
set the RCVR FIFO trigger levels, and select
the mode of DMA signaling.
Bit 0: Writing a 1 to this bit enables both the
XMIT and RCVR FIFO’s. When changing from
FIFO Mode to Character Mode and vice versa,
data is not automatically cleared from the
FIFO’s. This bit must be a 1 when writing to
other
programmed.
Bit 1: Writing a 1 to FCR1 will reset its
counters to 0, and then self clear this bit to 0.
The shift register is not cleared.
Bit 2: Functions the same as bit 1, except
for XMIT FIFO counters.
Bit 3: If FCR0=1, setting FCR# to a 1 will
cause the RXRDY and TXRDY pins to change
from mode 0 to mode 1 (see description of
RXRDY and TXRDY pins).
FCR
IMP16C552
IMP16C552
bits
or
they
INT0/1
will
not
be
© 2002 IMP, Inc.