IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 20

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

20
When
interrupts are enabled (FCR0=1, IER1=1),
XMIT interrupts will occur as follows:
A. The transmitter holding register interrupt
B. The transmitter FIFO empty indications
Character timeout and RCVR FIFO trigger
level interrupts have the same priority as the
current received data available interrupt; XMIT
FIFO empty has the same priority as the
current transmitter holding register empty
interrupt.
FIFO Polled Mode Operation
CPU reads the RCVR FIFO.
(02) occurs when the XMIT FIFO is empty;
it is cleared as soon as the transmitter
holding register is written to (1 to 16
characters may be written to this XMIT
FIFO while servicing this interrupt) or the
IIR is read.
will be delayed 1 character time minus
the last stop bit time whenever the
following occurs: THRE=1 and there have
not been at least tow bytes at the same
time in the transmit FIFO, since the last
THRE=1, The first transmitter interrupt
after changing FCR0 will be immediate, if
it is enabled.
the
XMIT
FIFO
and
transmitter
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With FCR0=1 RESETTING IER1, IER2,
IERR3 or all to zero puts the UART in the
RCVR
separately either one or both can be in the
polled mode of operation.
In this mode the users program will check
RCVR and XMITTED status via the LSR. As
stated previously:
LSR0 will be set as long as there is one byte
in the RCVR FIFO.
LSR1 to LSR4 will specify which error(s) has
occurred. Character error status is handled
the same way as when in the interrupt mode,
the IIR is not affected since IER2=0.
LSR5 will indicate when the XMIT FIFO is
empty.
LSR6 will indicate that both the XMIT FIFO
and shift register are empty.
LSR7 will indicate whether there are any
errors in the RCVR FIFO.
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode.
However, the RCVR and XMIT FIFO’s are still
fully capable of holding characters.
and
IMP16C552
IMP16C552
XMITTER
are
controlled
© 2002 IMP, Inc.