IMP16C554 IMP Inc, IMP16C554 Datasheet
IMP16C554
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IMP16C554 Summary of contents
Page 1
... The IMP16C554 provides internal loop-back capability for on board diagnostic testing. The IMP16C554 is fabricated in an advanced 1.2u CMOS process to achieve low drain power and high speed requirements. Pin Configuration DSRA• ...
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... I Serial data input. The serial information (data) received from serial port to IMP16C554 receive input circuit . A mark (high) is logic one and a space (low)is logic zero. During the local loopback mode the RX input is disabled from external connection and to the TX output internally. ...
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... Signal Pin Description Type O Transmit ready. (active low) This pin goes high when the transmit FIFO of the IMP16C554 is full. It can be used as a single or multi-transfer. I Address select line 2.To select internal registers. I Address select line 1.To select internal registers. I Address select line 0.To select internal registers. ...
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... VCC 13.30 VCC 47.64 4 IMP16C554 IMP16C554 Signal Type Pin Description This pin will be set to high state after writing a “0” to that register or after the reset. Note that this pin does not have any effect on the transmit or receive operation. I Master reset.(active high)A high on this pin will reset all the outputs and internal registers ...
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... IMP16C554 ACCESSIBLE REGISTERS A2A1A0 Registe BIT RHR bit THR bit IER FCR RCV R trigge r (MSB ) ISR 0/FIF Os enabl LCR Divis or latch enabl MCR LSR o/FIF O error MSR ...
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... FIFO reset when the FIFO is empty. FIFO POLLED MODE OPERATION When FCR BIT-0=1;resetting IER BIT 3-0 to zero puts the IMP16C554 in the FIFO polled mode of operation. Since the receiver and 408-432-9100/www.impweb.com IMP16C554 IMP16C554 ...
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... The IMP16C554 provides four level prioritized interrupt conditions to minimize software overhead during data character transfers. The interrupt Status Register (ISR) provides the source of the interrupt in prioritized matter. During the read cycle the IMP16C554 provides the highest interrupt level to be serviced by indicate when the CPU ...
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... Once active the TXRDY* pin will go high 8 IMP16C554 IMP16C554 (inactive) after the first character is loaded into the transmit holding register. Receive operation in mode “0”: When IMP16C554 is in IMP16C450 mode (FCR bit-0= the bit-1=1,FCR bit-3=0) and there is at least 1 character in the receive FIFO, the RXRDY* pin will go low ...
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... FIFOs are enabled. an overrun error will occur only after the FIFO is full and the next character has been completely received in the shift register. Note that character in the shift register is over written, but it is not transferred to the FIFO. 408-432-9100/www.impweb.com IMP16C554 IMP16C554 © 2002 IMP, Inc. ...
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... Indicates that the DSR* input to the IMP16C554 has changed state since the last time it was read. MSR BIT-2: Indicates that the RI* input to the IMP16C554 has changed from a low to a high state. MSR BIT-3: Indicates that the CD* input to the ST16C554 has changed state since the last time it was read ...
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... IMP16C554 EXTERNAL RESET CONDITION REGISTER RESET STATE IER IER BIT 0-7=0 ISR ISR BIT-0=1, ISR BIT 1-7=0 LCR LCR BITS 0-7=0 MCR MCR BITS 0-7=0 LSR LSR BITS 0-4=0, LSR BITS 5-6=1 LSR,BIT AC ELECTRICAL CHARACTERISTICS 0 TA=0 –70 C,Vcc= 5.0V±10% unless otherwise specified Symbol Parameter T1 Clock high pulse duration ...
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... Clock input high level VIL input low level VIH input high level VOL Output low level on all outputs VOH output high level ICC Avg power supply current 12 IMP16C554 IMP16C554 7 Volts GND-0 VCC 150 C 500 Mw ...
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... A0-A2 T8 CSx* T21 IOR* D0-D7 A0-A2 T8 CSx* T14 IOW* D0- T23 T24 T25 T19 T26 FIGURE 1 - GENERAL READ TIMING T9 T15 T16 T17 T13 T12 FIGURE 2 - GENERAL WRITE TIMING 408-432-9100/www.impweb.com IMP16C554 IMP16C554 162450-RD-1 162450-WD-1 © 2002 IMP, Inc. ...
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... IOW* RTS* DTR* CD CTS DSR INTx IOR* RI EXTERNAL CLOCK CLOCK PERIOD 14 T28 T29 T29 T30 FIGURE 3 - MODEM TIMING T2 T1 CLOCK PERIOD FIGURE 4 - CLOCK TIMING 408-432-9100/www.impweb.com IMP16C554 IMP16C554 T29 162450-MD 161450-CK-1 © 2002 IMP, Inc. ...
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... START BIT DATA BITS£¨5-8£© DATA BITS 6 DATA BITS 7 DATA BITS T33 16 BAUD RATE CLOCK FIGURE 5 408-432-9100/www.impweb.com IMP16C554 IMP16C554 STOP BIT D7 PARITY BIT NEXT DATA START BIT T34 T35 162450-TX-1 © 2002 IMP, Inc. ...
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... RXRDY* IOR* 16 DATA BITS£¨5-8£© DATA BITS PARITY BIT 6 DATA BITS 7 DATA BITS FIGURE 6 - RXRDY TIMING FOR MODE "0" 408-432-9100/www.impweb.com IMP16C554 IMP16C554 STOP BIT T44 T45 16552-RX-2 © 2002 IMP, Inc. ...
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... DATA BITS£¨5-8£© DATA BITS PARITY BIT 6 DATA BITS 7 DATA BITS FIGURE 7 - RXRDY TIMING FOR MODE "1" 408-432-9100/www.impweb.com IMP16C554 IMP16C554 STOP BIT First byte that reaches the trigger level T44 T45 16552-RX-3 © 2002 IMP, Inc. ...
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... START BIT DATA BITS£¨5-8£© DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK FIGURE 8 - RECEIVE TIMING 408-432-9100/www.impweb.com IMP16C554 IMP16C554 STOP BIT D7 PARITY BIT NEXT DATA START BIT T31 T32 162450-RX-1 © 2002 IMP, Inc. ...
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... START BIT TX IOW* D0-D7 TXRDY* 19 DATA BITS£¨5-8£© DATA BITS 6 DATA BITS 7 DATA BITS BYTE#1 T46 FIGURE 9 - TXRDY TIMING FOR MODE "0" 408-432-9100/www.impweb.com IMP16C554 IMP16C554 STOP BIT D7 PARITY BIT T47 16552-TX-2 © 2002 IMP, Inc. ...
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... DATA BITS 6 DATA BITS 7 DATA BITS BYTE#16 T46 FIGURE 10 - TXRDY TIMING FOR MODE "1" Package Operating Temperature PLCC 68pins 0 to +70 PLCC 68pins -40 to +85 408-432-9100/www.impweb.com IMP16C554 IMP16C554 STOP BIT PARITY BIT T47 FIFO FULL 16552-TX-3 © 2002 IMP, Inc. ...