HT48CU80 Holtek Semiconductor, HT48CU80 Datasheet - Page 29

• Manufacturer Part Number: HT48CU80
• Description: (HT48RU80 / HT48CU80) I/O Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

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Rev. 1.00
UART receiver
It should be noted that when TXIF=0, data will be in-
hibited from being written to the TXR register. Clear-
ing the TXIF flag is always achieved using the
following software sequence:
The read-only TXIF flag is set by the UART hard-
ware and if set indicates that the TXR register is
empty and that other data can now be written into
the TXR register without overwriting the previous
data. If the TEIE bit is set then the TXIF flag will gen-
erate an interrupt.
During a data transmission, a write instruction to the
TXR register will place the data into the TXR regis-
ter, which will be copied to the shift register at the
end of the present transmission. When there is no
data transmission in progress, a write instruction to
the TXR register will place the data directly into the
shift register, resulting in the commencement of
data transmission, and the TXIF bit being immedi-
ately set. When a frame transmission is complete,
which happens after stop bits are sent or after the
break frame, the TIDLE bit will be set. To clear the
TIDLE bit the following software sequence is used:
Note that both the TXIF and TIDLE bits are cleared
by the same software sequence.
Transmit break
If the TXBRK bit is set then break characters will be
sent on the next transmission. Break character
transmission consists of a start bit, followed by 13
N 0 bits and stop bits, where N=1, 2, etc. If a break
character is to be transmitted then the TXBRK bit
must be first set by the application program, then
cleared to generate the stop bits. Transmitting a
break character will not generate a transmit inter-
rupt. Note that a break condition length is at least 13
bits long. If the TXBRK bit is continually kept at a
logic high level then the transmitter circuitry will
transmit continuous break characters. After the ap-
plication program has cleared the TXBRK bit, the
transmitter will finish transmitting the last break
character and subsequently send out one or two
stop bits. The automatic logic highs at the end of the
last break character will ensure that the start bit of
the next frame is recognized.
Introduction
The UART is capable of receiving word lengths of ei-
ther 8 or 9 bits. If the BNO bit is set, the word length
will be set to 9 bits with the MSB being stored in the
RX8 bit of the UCR1 register. At the receiver core lies
1. A USR register access
2. A TXR register write execution
1. A USR register access
2. A TXR register write execution
Set the TXEN bit to ensure that the TX pin is used
as a UART transmitter pin and not as an I/O pin.
Access the USR register and write the data that is
to be transmitted into the TXR register. Note that
this step will clear the TXIF bit.
This sequence of events can now be repeated to
send additional data.
29
the Receive Serial Shift Register, commonly known
as the RSR. The data which is received on the RX
external input pin, is sent to the data recovery block.
The data recovery block operating speed is 16 times
that of the baud rate, while the main receive serial
shifter operates at the baud rate. After the RX pin is
sampled for the stop bit, the received data in RSR is
transferred to the receive data register, if the register
is empty. The data which is received on the external
RX input pin is sampled three times by a majority de-
tect circuit to determine the logic level that has been
placed onto the RX pin. It should be noted that the
RSR register, unlike many other registers, is not di-
rectly mapped into the Data Memory area and as
such is not available to the application program for
direct read/write operations.
When the UART receiver is receiving data, the data
is serially shifted in on the external RX input pin,
LSB first. In the read mode, the RXR register forms
a buffer between the internal bus and the receiver
shift register. The RXR register is a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO while a third byte can continue to be received.
Note that the application program must ensure that
the data is read from RXR before the third byte has
been completely shifted in, otherwise this third byte
will be discarded and an overrun error OERR will be
subsequently indicated. The steps to initiate a data
transfer can be summarized as follows:
At this point the receiver will be enabled which will
begin to look for a start bit.
When a character is received the following se-
quence of events will occur:
The RXIF bit can be cleared using the following
software sequence:
Any break character received by the UART will be
managed as a framing error. The receiver will count
and expect a certain number of bit times as speci-
fied by the values programmed into the BNO and
Receiving data
Receive break
1. A USR register access
2. An RXR register read execution
Make the correct selection of BNO, PRT, PREN
and STOPS bits to define the word length, parity
type and number of stop bits.
Setup the BRG register to select the desired baud
rate.
Set the RXEN bit to ensure that the RX pin is used
as a UART receiver pin and not as an I/O pin.
The RXIF bit in the USR register will be set when
RXR register has data available, at least one
more character can be read.
When the contents of the shift register have been
transferred to the RXR register, then if the RIE bit
is set, an interrupt will be generated.
If during reception, a frame error, noise error, par-
ity error, or an overrun error has been detected,
then the error flags can be set.
HT48RU80/HT48CU80
April 12, 2006