HT48CU80 Holtek Semiconductor, HT48CU80 Datasheet - Page 14

• Manufacturer Part Number: HT48CU80
• Description: (HT48RU80 / HT48CU80) I/O Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

www.DataSheet4U.com
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibbles and bit 3 of the WDTS
are reserved for users defined flags, which can be used
to indicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) or 32kHz crystal oscil-
lator (RTC OSC) is strongly recommended, since the
HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset
and only the Program Counter and SP are reset to zero.
To clear the WDT contents (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a HALT in-
struction. The software instruction include CLR WDT
and the other set
these two types of instruction, only one can be active de-
pending on the option
tion . If the CLR WDT is selected (i.e. CLRWDT times
equal one), any execution of the CLR WDT instruction
will clear the WDT. In the case that CLR WDT1 and
two), these two instructions must be executed to clear
the WDT, otherwise, the WDT may reset the chip as a
result of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
Rev. 1.00
CLR WDT2 are chosen (i.e. CLRWDT times equal
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WDTS Register
CLR WDT1 and CLR WDT2 . Of
WS0
CLR WDT times selection op-
0
1
0
1
0
1
0
1
Division Ratio
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
14
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the cause for a chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the CLR WDT instruction and is set when exe-
cuting the HALT instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP; the others remain
in their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in Port A can be independently selected to wake-up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The RTC oscillator still runs in the HALT mode (if the
RTC oscillator is enabled).
Reset
There are three ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the initial condition when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
1 before entering the HALT mode, the wake-up func-
chip resets .
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
HT48RU80/HT48CU80
SYS
April 12, 2006
(system clock