HT48CU80 Holtek Semiconductor, HT48CU80 Datasheet - Page 11

• Manufacturer Part Number: HT48CU80
• Description: (HT48RU80 / HT48CU80) I/O Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

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give different results from those intended. The TO
flag can be affected only by a system power-up, a
WDT time-out or executing the ²CLR WDT² or
²HALT² instruction. The PDF flag can be affected
only by executing the ²HALT² or ²CLR WDT² instruc-
tion or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The device provides two external interrupts, three inter-
nal timer/event counter interrupts, and a UART TX/ RX
interrupt. The Interrupt Control Register 0 (INTC0; 0BH)
and Interrupt Control Register 1 (INTC1;1EH) both con-
tain the interrupt control bits that are used to set the en-
able/disable status and interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 or INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decre-
mented. If immediate service is desired, the stack must
be prevented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
Rev. 1.00
Bit No.
6~7
0
1
2
3
4
5
Label
PDF
AC
OV
TO
¾
C
Z
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
Unused bit, read as ²0².
Status (0AH) Register
11
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of the INT0 or INT1 and the related interrupt request
flag (EIF0; bit 4 of the INTC0; EIF1; bit 4 of the INTC1)
will be set. When the interrupt is enabled, the stack is
not full and the external interrupt is active, a subroutine
call to location 04H or 10H will occur. The interrupt re-
quest flag (EIF0 or EIF1) and EMI bits will be cleared to
disable other interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of the INTC0), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
The internal Timer/Event Counter 1 interrupt is initial-
ized by setting the Timer/Event Counter 1 interrupt re-
quest flag (T1F; bit 6 of the INTC0), caused by a T 1
overflow. When the interrupt is enabled, the stack is not
full and the T1F is set, a subroutine call to location 0CH
will occur. The related interrupt request flag (T1F) will be
reset and the EMI bit cleared to disable further inter-
rupts.
The UART interrupt is initialized by setting the interrupt
request flag (URF; bit 5 of the INTC1), that is caused by
a regular UART receive signal, caused by a UART
transmit signal. After the interrupt is enabled, the stack
is not full, and the URF bit is set, a subroutine call to lo-
cation 14H occurs. The related interrupt request flag
(URF) is reset and the EMI bit is cleared to disable fur-
ther other interrupts.
Function
HT48RU80/HT48CU80
April 12, 2006