HT48CU80 Holtek Semiconductor, HT48CU80 Datasheet - Page 12

• Manufacturer Part Number: HT48CU80
• Description: (HT48RU80 / HT48CU80) I/O Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

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The internal Timer/Event Counter 2 interrupt is initial-
ized by setting the Timer/Event Counter 2 interrupt re-
quest flag (T2F; bit 6 of the INTC1), caused by a T 2
overflow. When the interrupt is enabled, the stack is not
full and the T2F is set, a subroutine call to location 18H
will occur. The related interrupt request flag (T2F) will be
reset and the EMI bit cleared to disable further inter-
rupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
Rev. 1.00
Bit No.
Bit No.
3, 7
0
1
2
3
4
5
6
7
0
1
2
4
5
6
Label
Label
EURI
EEI0
ET0I
ET1I
EIF0
EEI1
ET2I
EIF1
URF
EMI
T0F
T1F
T2F
Controls the master (global) interrupt (1= enable; 0= disable)
Controls the external interrupt 0 (1= enable; 0= disable)
Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)
Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable)
External interrupt 0 request flag (1= active; 0= inactive)
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
Unused bit, read as 0
Controls the external interrupt 1 (1= enable; 0= disable)
Controls the UART TX or RX interrupt (1= enable; 0= disable)
Controls the Timer/Event Counter 2 overflow interrupt (1= enable; 0= disable)
Unused bit, read as 0
External interrupt 1 request flag (1= active; 0= inactive)
UART TX or RX interrupt request flag (1= active; 0= inactive)
Timer/Event Counter 2 overflow request flag (1= active; 0= inactive)
INTC0 (0BH) Register
INTC1 (1EH) Register
12
These can be masked by resetting the EMI bit.
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), external interrupt 0 request flag (EIF0), en-
able Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I),
enable external interrupt 0 bit (EEI0) and enable master
interrupt bit (EMI ) constitute an interrupt control register
(INTC0) which is located at 0BH in the data memory.
EMI, EEI0, ET0I and ET1I are used to control the en-
abling or disabling of interrupts. These bits prevent the
requested interrupt from being serviced. Once the inter-
rupt request flags (T0F, T1F, EIF0) are set, they will re-
main in the INTC0 register until the interrupts are
serviced or cleared by a software instruction.
No.
a External Interrupt 0
b Timer/Event Counter 0 Overflow
d External Interrupt 1
e UART Interrupt
c Timer/Event Counter 1 Overflow
f
Function
Function
Timer/Event Counter 2 Overflow
Interrupt
Interrupt Source
HT48RU80/HT48CU80
Priority Vector
April 12, 2006
1
2
3
4
5
6
010H
014H
018H
0CH
04H
08H