HT48CU80 Holtek Semiconductor, HT48CU80 Datasheet
HT48CU80
Related parts for HT48CU80
HT48CU80 Summary of contents
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... SSOP, 64-pin QFP package wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem con- trollers, etc. The HT48CU80 is under development and will be avail- able soon. 1 April 12, 2006 ...
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... Block Diagram www.DataSheet4U.com Rev. 1.00 HT48RU80/HT48CU80 2 April 12, 2006 ...
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... Pin Assignment www.DataSheet4U.com Rev. 1.00 HT48RU80/HT48CU80 3 April 12, 2006 ...
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... RC oscillator whose nominal frequency at 5V has 4 options, 3.2MHz, 1.6MHz, 800kHz, 400kHz. Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground. 0. +6.0V Storage Temperature ............................ 125 0. +0.3V Operating Temperature........................... HT48RU80/HT48CU80 Description April 12, 2006 ...
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... No load, f SYS 3V No load, system HALT load, system HALT load, system HALT 5V LVR enabled 3V V =0. =0. =0. =0. HT48RU80/HT48CU80 Ta=25 C Min. Typ. Max. Unit 2.2 5.5 V 3.3 5.5 V 0.6 1.5 mA =4MHz 0.8 1.5 mA =4MHz 2 =8MHz ...
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... Conditions DD 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3.2MHz 1.6MHz 5V 800kHz 400kHz 2.2V~5.5V 3.3V~5. Without WDT prescaler 5V Without WDT prescaler Without WDT prescaler Wake-up from HALT 6 HT48RU80/HT48CU80 Ta=25 C Min. Typ. Max. Unit 400 4000 kHz 400 8000 kHz 400 4000 kHz 400 8000 kHz 1800 5400 kHz 900 2700 kHz ...
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... Program Counter+2 *13 *12 *11 * BP.5 #12 #11 # S13 S12 S11 S10 Program Counter S13~S0: Stack register bits @7~@0: PCL bits 7 HT48RU80/HT48CU80 * ...
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... Table Location P13~P8: Current program counter bits 8 HT48RU80/HT48CU80 Location 000H This area is reserved for program initialization. After a chip reset, the program always begins execution at lo- cation 000H. Location 004H This area is reserved for the external interrupt 0 ser- vice program. If the INT0 interrupt pin is activated, the interrupt enabled and the stack is not full, the program begins execution at location 004H ...
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... Accumulator - ACC The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations. The data RAM Bank movement between two data memory locations must 0 pass through the accumulator HT48RU80/HT48CU80 April 12, 2006 ...
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... Branch decision (SZ, SNZ, SIZ, SDZ) The ALU not only saves the results of a data operation but also changes the status register. Rev. 1.00 HT48RU80/HT48CU80 RAM Mapping Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO) ...
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... After the interrupt is enabled, the stack is not full, and the URF bit is set, a subroutine call to lo- cation 14H occurs. The related interrupt request flag (URF) is reset and the EMI bit is cleared to disable fur- ther other interrupts. 11 HT48RU80/HT48CU80 April 12, 2006 ...
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... These bits prevent the requested interrupt from being serviced. Once the inter- rupt request flags (T0F, T1F, EIF0) are set, they will re- main in the INTC0 register until the interrupts are serviced or cleared by a software instruction. 12 HT48RU80/HT48CU80 Interrupt Source Priority Vector 1 04H 2 ...
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... OSC2, which can be used to synchro- nize external logic. The RC oscillator provides the most Rev. 1.00 HT48RU80/HT48CU80 cost effective solution. However, the frequency of os- cillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suit- able for timing sensitive operations where an accurate oscillator frequency is desired ...
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... Some regis- ters remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets . 14 HT48RU80/HT48CU80 (system clock SYS April 12, 2006 ...
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... Disable Clear Clear. After master reset, WDT begins counting Input mode Points to the top of the stack 15 HT48RU80/HT48CU80 Reset Circuit * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart Reset Configuration April 12, 2006 ...
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... HT48RU80/HT48CU80 RES Reset WDT Time-out (HALT) (HALT)* xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 00-0 1--- uu-u u--- xxxx xxxx uuuu uuuu ...
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... TMR1H and TMR1L preload registers, respectively. The Timer/Event Coun- ter 1 preload register is changed by each writing opera- Rev. 1.00 HT48RU80/HT48CU80 tions to the TMR1H. Reading from the TMR1H will latch the contents of TMR1H and TMR1L counters to the des- tination and the lower-order byte buffer, respectively. ...
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... Enables or disables the timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR2C (22H) Register 18 HT48RU80/HT48CU80 April 12, 2006 ...
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... No matter what the op- eration mode is, writing ET0I/ET1I/ET2I can dis- www.DataSheet4U.com Rev. 1.00 HT48RU80/HT48CU80 able the corresponding interrupt services. In the case of Timer/Event Counter 0/1/2 OFF condition, writing data to the Timer/Event Counter 0/1/2 preload register will also reload that data to the Timer/Event Counter 0/1/2. ...
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... There is a pull-high option available for all I/O lines (port option). Once the pull-high option of an I/O line is se- lected, the I/O line has a pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. PA, PB, PC2~PC7, PD, PE, PF, PG Input/Output Ports 20 HT48RU80/HT48CU80 April 12, 2006 ...
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... The LVR uses an OR function with the external RES signal to perform a chip reset. Rev. 1.00 PC0/TX Input/Output Ports PC1/RX Input/Output Ports The relationship between V ) has to remain in its origi- LVR Note: V OPR tion at 4MHz system clock. 21 HT48RU80/HT48CU80 and V is shown below. DD LVR is the voltage range for proper chip opera- April 12, 2006 ...
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... Since the low voltage has to maintain its original state for longer than 1ms, therefore a 1ms delay enters the reset mode. UART Bus Serial Interface The HT48RU80/HT48CU80 devices contain an inte- grated full-duplex asynchronous serial communications UART interface that enables communication with exter- nal devices that contain a serial interface ...
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... When TIDLE is 1 the TX pin becomes idle. The TIDLE flag is cleared by reading the USR regis- Rev. 1.00 HT48RU80/HT48CU80 UART Data Transfer Scheme ter with TIDLE set and then writing to the TXR regis- ter. The flag is not generated when a data character break is queued and ready to be sent ...
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... USR status register, followed by an ac- cess to the RXR data register. Rev. 1.00 HT48RU80/HT48CU80 UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc ...
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... When the bit is 1 the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN control bits. When the UART is Rev. 1.00 HT48RU80/HT48CU80 disabled it will empty the buffer so any character re- maining in the buffer will be discarded. In addition, the baud rate counter value will be reset. When the UART is disabled, all error and status flags will be reset ...
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... TXEN bit is equal to 1 the transmitter will be enabled and if the UARTEN bit is equal to 1 the Rev. 1.00 HT48RU80/HT48CU80 TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the trans- mission to be aborted and will reset the transmitter. ...
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... Baud Rates and Error Values for BRGH = 1 27 HT48RU80/HT48CU80 f =4MHz f =3.579545MHz SYS SYS BRG Kbaud Error BRG Kbaud Error 207 0.300 0.00 185 0.300 51 1.202 0.16 46 1.19 -0.83 25 2.404 0.16 22 2.432 12 4.808 0.16 11 4.661 6 8 ...
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... HT48RU80/HT48CU80 UART transmitter Data word lengths of either bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register ...
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... MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies Rev. 1.00 HT48RU80/HT48CU80 the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. ...
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... The RXR contents will not be lost. The shift register will be overwritten. An interrupt will be generated if the RIE bit is set. Rev. 1.00 HT48RU80/HT48CU80 The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Noise Error - NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise ...
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... If the ADDEN bit is not enabled, then a Receiver Data Avail- able interrupt will be generated each time the RXIF Rev. 1.00 HT48RU80/HT48CU80 UART Interrupt Scheme flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions ...
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... PBC Register PB Data Register PBC1 PB0 PB0/PB1 Pin Function Control 32 HT48RU80/HT48CU80 PB Data Register Output Function PB1 PB0 PB1= 0 PB0=BZ X PB1=BZ PB0 PB1=input line PB0=BZ X PB1=input line PB0=input line X PB1=BZ PB0=input line X ...
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... Ext. RC, Ext. crystal, Int. RC+RTC 9 Buzzer output enable: enabled or disabled 10 Buzzer clock selection: TMR0 or TMR1 11 Int. RC frequency selection: 3.2MHz, 1.6MHz, 800kHz or 400kHz 12 LVR enable or disable Rev. 1.00 HT48RU80/HT48CU80 Options /4 or RTC oscillator or disable SYS /4 or RTCOSC SYS /4 or RTCOSC SYS 33 April 12, 2006 ...
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... The function of the resistor ensure that the oscillator will switch off should low voltage condi- tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Rev. 1.00 Crystal or Resonator 34 HT48RU80/HT48CU80 C1 0pF 10k 10pF ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 HT48RU80/HT48CU80 Instruction Description 35 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT48RU80/HT48CU80 Instruction Description 36 Flag Cycle Affected 2 None (2) 1 ...
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... The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x TO PDF Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO PDF Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... TO and PDF flags remain unchanged. WDT 00H* PDF and PDF Complement data memory Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... TO PDF Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. ACC [ PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr TO PDF Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... ACC PDF Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m] 1)=0, ACC ([ PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Skip if [m]. PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... ACC XOR [m] TO PDF Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x TO PDF HT48RU80/HT48CU80 April 12, 2006 ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions www.DataSheet4U.com Symbol Rev. 1.00 HT48RU80/HT48CU80 Dimensions in mil Min. Nom. 395 291 8 613 Max. 420 299 12 637 April 12, 2006 ...
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... QFP (14´20) Outline Dimensions www.DataSheet4U.com Symbol Rev. 1.00 HT48RU80/HT48CU80 Dimensions in mm Min. Nom. 18.80 13.90 24.80 19.90 1 0.40 2.50 0.10 1.15 0. Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.45 0.20 7 April 12, 2006 ...
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... Product Tape and Reel Specifications Reel Dimensions www.DataSheet4U.com SSOP 48W Symbol A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Description 52 HT48RU80/HT48CU80 Dimensions in mm 330 1.0 100 0.1 13.0+0.5 0.2 2.0 0.5 32.2+0.3 0.2 38.2 0.2 April 12, 2006 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Description 53 HT48RU80/HT48CU80 Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.1 14.2 0.1 2.0 Min. 1.5+0.25 4.0 0.1 2.0 0.1 12.0 0.1 16.20 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 April 12, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT48RU80/HT48CU80 54 April 12, 2006 ...