HT48CU80 Holtek Semiconductor, HT48CU80 Datasheet - Page 17

• Manufacturer Part Number: HT48CU80
• Description: (HT48RU80 / HT48CU80) I/O Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

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Timer/Event Counter
Three timer/event counters (TMR0, TMR1, TMR2) are
implemented in this microcontroller.
The Timer/Event Counter 0 contains a 16-bit program-
mable count-up counter and the clock may come from
an external source or from the system clock divided by 4
or RTC.
The Timer/Event Counter 1 contains a 16-bit program-
mable count-up counter and the clock may come from
an external source or from the system clock divided by 4
or RTC.
The Timer/Event Counter 2 contains an 8-bit program-
mable count-up counter and the clock may come from
an external source or from the system clock or RTC.
Using the internal clock sources, there are two refer-
ence time-bases for the Timer/Event Counter 0. The in-
ternal clock source can be selected as coming from
f
by a system oscillator in the Int. RC+RTC mode) by op-
tions.
Using the internal clock sources, there are two refer-
ence time-bases for the Timer/Event Counter 1. The in-
ternal clock source can be selected as coming from
f
by a system oscillator in the Int. RC+RTC mode) by op-
tions.
Using external clock input allows the user to count exter-
nal events, measure time internals or pulse widths, or
generate an accurate time base. While using the inter-
nal clock allows the user to generate an accurate time
base.
There are three registers related to the Timer/Event
Counter 0, namely, TMR0H ([0CH]), TMR0L ([0DH]),
and TMR0C ([0EH]). Writing to the TMR0L will only put
the written data to an internal lower-order byte buffer (8
bits) and writing to the TMR0H will transfer the specified
data and the contents of the lower-order byte buffer to
TMR0H and TMR0L preload registers, respectively. The
Timer/Event Counter 0 preload register is changed by
each writing operations to theTMR0H. Reading from the
TMR0H will latch the contents of the TMR0H and
TMR0L counters to the destination and the lower-order
byte buffer, respectively. Reading the TMR0L will read
the contents of the lower-order byte buffer. The TMR0C
is the Timer/Event Counter 0 control register, which de-
fines the operating mode, counting enable or disable
and active edge.
There are three registers related to the Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).
Writing to the TMR1L will only put the written data to an
internal lower-order byte buffer (8 bits) and writing to the
TMR1H will transfer the specified data and the contents
of the lower-order byte buffer to TMR1H and TMR1L
preload registers, respectively. The Timer/Event Coun-
ter 1 preload register is changed by each writing opera-
Rev. 1.00
SYS
SYS
/4 (can always be optioned) or RTC (enabled only
/4 (can always be optioned) or RTC (enabled only
17
tions to the TMR1H. Reading from the TMR1H will latch
the contents of TMR1H and TMR1L counters to the des-
tination and the lower-order byte buffer, respectively.
Reading the TMR1L will read the contents of the
lower-order byte buffer. The TMR1C is the Timer/Event
Counter 1 control register, which defines the operating
mode, counting enable or disable and active edge.
There are two registers related to timer/event counter,
namely, TMR2 (21H) and TMR2C (22H). In the
timer/event counter counting mode (T2ON=1), writing
TMR2 will only put the written data to the preload regis-
ter (8 bits). The timer/event counter preload register is
changed by each writing operations to the TMR2. Read-
ing from the TMR2 will also latch the TMR2 to the desti-
nation. The TMR2C is the timer/event counter control
register, which defines the operating mode, counting en-
able or disable and active edge.
The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C),
T2M0, T2M1 (TMR2C) bits define the operating mode.
The event count mode is used to count external events,
which means the clock source comes from an external
pin (TMR0/TMR1/TMR2). The timer mode functions as
a normal timer with the clock source coming from the in-
struction clock or RTC clock (Timer0/Timer1/Timer2).
The pulse width measurement mode can be used to
count the high or low level duration of the external signal
(TMR0/TMR1/TMR2). The counting is based on the in-
struction clock or RTC clock (Timer0/Timer1/Timer2).
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contents in the Timer/Event Counter 0/1 to FFFFH.
Once overflow occurs, the counter is reloaded from the
Timer/Event Counter 0/1 preload register and at the
same time generates the interrupt request flag
(T0F/T1F; bit 5/6 of the INTC0).
In the event count or timer mode, once the Timer/Event
Counter 2 starts counting, it will count from the current
contents in the timer/event counter to FFH. Once over-
flow occurs, the counter is reloaded from the
Timer/Event Counter 2 preload register and at the same
time generates the corresponding interrupt request flag
(T2F; bit 6 of the INTC1).
In the pulse width measurement mode with the T0ON/
T1ON/T2ON and T0E/T1E/T2E bits equal to one, once
the TMR0/TMR1/TMR2 has received a transient from
low to high (or high to low if the T0E/T1E/T2E bits are
turns to the original level and resets the T0ON/T1ON/
T2ON. The measured result will remain in the
Timer/Event Counter 0/1/2 even if the activated tran-
sient occurs again. In other words, only one cycle mea-
surement can be done. Until setting the T0ON/T1ON/
T2ON, the cycle measurement will function again as
long as it receives further transient pulse. Note that, in
this operating mode, the Timer/Event Counter 0/1/2
starts counting not according to the logic level but ac-
0 ) it will start counting until the TMR0/TMR1/ TMR2 re-
HT48RU80/HT48CU80
April 12, 2006