IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 37

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
WCLK
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
WCLK
RCLK
RCLK
WEN
WEN
REN
REN
PAE
HF
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
[
D-1
n + 1 words in FIFO
t
2
CLKH
D/2 words in FIFO
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
n words in FIFO
+ 1
]
words in FIFO
t
CLKH
(1)
(2) ,
,
(2)
(3)
t
t
ENS
ENS
TM
t
CLKL
36-BIT FIFO
t
CLKL
37
t
ENH
t
t
ENH
PAEA
t
HF
t
ENS
t
ENS
[
n + 1 words in FIFO
n + 2 words in FIFO
D/2 + 1 words in FIFO
D-1
2
+ 2
]
words in FIFO
t
PAEA
t
HF
(2) ,
(3)
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
n + 1 words in FIFO
[
TEMPERATURE RANGES
D-1
n words in FIFO
2
D/2 words in FIFO
+ 1
]
words in FIFO
APRIL 6, 2006
6117 drw27
6117 drw26
(2) ,
(1)
,
(3)
(2)