IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 21

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Q
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Q
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
WRITE STROBE & WRITE CLOCK (WR/WCLK)
input behaves as WCLK.
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE ( WEN )
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
cycle.
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + t
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +
t
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE
and HF flags will not be updated. (Note that RCLK is only capable of updating
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
SKEW
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF
If Synchronous operation of the write port has been selected via ASYW, this
A write cycle is initiated on the rising edge of the WCLK input. Data setup
If Asynchronous operation has been selected this input is WR (write strobe).
When the WEN input is LOW, data may be loaded into the FIFO RAM array
When WEN is HIGH, no new data is written in the RAM array on each WCLK
To prevent data overflow in the IDT Standard mode, FF will go LOW,
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
If Asynchronous operation of the write port has been selected, then WEN
If Synchronous operation of the read port has been selected via ASYR, this
after the valid RCLK cycle.
SKEW
after the RCLK cycle.
n)
. It also uses Input Ready (IR) to indicate
n
after three RCLK
TM
36-BIT FIFO
21
the HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
Strobe) . Data is Asynchronously read from the FIFO via the output register
whenever there is a rising edge on RD. In this mode the REN input must be
tied LOW. The OE input is used to provide Asynchronous control of the three-
state Qn outputs.
READ ENABLE ( REN )
register on the rising edge of every RCLK cycle if the device is not empty.
and no new data is loaded into the output register. The data outputs Q
maintain the previous data value.
word written to an empty FIFO, must be requested using REN. When the last
word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting
further read operations. REN is ignored when the FIFO is empty. Once a write
is performed, EF will go HIGH allowing a read to occur. The EF flag is updated
by two RCLK cycles + t
to the outputs Q
after the first write. REN does not need to be asserted LOW. In order to access
all other words, a read must be executed using REN. The RCLK LOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read
operations. REN is ignored when the FIFO is empty.
must be held active, (tied LOW).
SERIAL ENABLE ( SEN )
registers. The serial programming method must be selected during Master
Reset. SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of WCLK.
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE ( OE )
data from the output register. When OE is HIGH, the output data bus (Q
into a high impedance state.
LOAD ( LD )
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset, LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values.
If Asynchronous operation has been selected this input is RD (Read
When Read Enable is LOW, data is loaded from the RAM array into the output
When the REN input is HIGH, the output register holds the previous data
In the IDT Standard mode, every word accessed at Q
In the FWFT mode, the first word written to an empty FIFO automatically goes
If Asynchronous operation of the Read port has been selected, then REN
The SEN input is an enable used only for serial programming of the offset
When SEN is HIGH, the programmable registers retains the previous
When Output Enable is enabled (LOW), the parallel output buffers receive
This is a dual purpose pin. During Master Reset, the state of the LD input,
After Master Reset, the LD pin is used to activate the programming process
n
, on the third valid LOW-to-HIGH transition of RCLK + t
SKEW
after the valid WCLK cycle.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
n
, including the first
APRIL 6, 2006
n
) goes
SKEW
0
-Q
n