IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 16

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
D/Q17
D/Q35
D/Q35
1st Parallel Offset Write/Read Cycle
D/Q17
2nd Parallel Offset Write/Read Cycle
D/Q16
16
D/Q16
IDT72V36100 ⎯
16
16
15
16
15
IDT72V36100/IDT72V36110 ⎯ x36 Bus Width
14
15
D/Q19
D/Q19
EMPTY OFFSET (LSB) REGISTER (PAE)
14
15
14
13
FULL OFFSET (LSB) REGISTER (PAF)
17
17
13
14
D/Q17
13
12
D/Q17
13
12
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
11
12
17
16
17
16
Data Inputs/Outputs
11
12
EMPTY OFFSET REGISTER (PAE)
11
10
15
16
FULL OFFSET REGISTER (PAF)
16
15
11
10
10
14
15
9
14
15
10
D/Q8
x18 Bus Width
9
14
13
14
13
9
D/Q8
9
13
12
8
12
13
8
8
8
12
11
12
11
7
7
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
7
7
11
10
6
11
6
10
# of Bits Used
6
6
10
5
5
10
9
9
D/Q8
5
5
D/Q8
4
9
4
9
4
4
3
3
8
8
8
8
3
3
2
2
7
7
7
7
# of Bits Used
# of Bits Used
D/Q0
2
2
1
1
6
6
6
6
D/Q0
1
1
5
5
5
5
Interspersed
Parity
Non-Interspersed
Parity
4
4
4
4
3
3
3
3
TM
2
2
2
2
36-BIT FIFO
D/Q0
D/Q0
1
1
1
1
Non-Interspersed
Parity
Non-Interspersed
Parity
Interspersed
Parity
Interspersed
Parity
16
D/Q17
D/Q17 D/Q16
D/Q17
D/Q17 D/Q16
1st Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q16
D/Q16
16
16
15
16
15
16
15
14
15
14
FULL OFFSET (MSB) REGISTER (PAF)
EMPTY OFFSET (LSB) REGISTER (PAE)
FULL OFFSET (LSB) REGISTER (PAF)
EMPTY OFFSET (MSB) REGISTER (PAE)
13
14
14
13
13
12
IDT72V36110 ⎯
13
12
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
12
11
12
11
10
11
11
10
10
10
9
9
D/Q8
D/Q8
9
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
9
8
8
8
8
7
7
7
7
6
6
COMMERCIAL AND INDUSTRIAL
6
6
x18 Bus Width
# of Bits Used
5
5
5
5
4
4
4
4
3
3
TEMPERATURE RANGES
3
3
2
2
2
2
D/Q0
D/Q0
D/Q0
D/Q0
17
17
17
17
1
1
1
1
APRIL 6, 2006
Interspersed
Parity
Non-Interspersed
Parity
6117 drw07