IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 33

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
Q
WCLK
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
0
RCLK
WEN
1
REN
PAE
- Q
PAF
= first word written to the FIFO after Master Reset, W
HF
EF
RT
n
t
ENS
W
x
t
A
t
ENS
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
W
t
RTS
x+1
2
= second word written to the FIFO after Master Reset.
1
t
A
t
t
ENH
HF
t
SKEW2
1
TM
36-BIT FIFO
W
1 (3)
33
2
t
PAFS
2
t
A
W
2 (3)
3
t
t
PAES
A
COMMERCIAL AND INDUSTRIAL
W
TEMPERATURE RANGES
3 (3)
APRIL 6, 2006
6117 drw18
t
t
ENH
A
W
4