IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet
IDT72V36110
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IDT72V36110 Summary of contents
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... Choose among the following memory organizations: IDT72V36100 ⎯ ⎯ ⎯ ⎯ ⎯ 65,536 x 36 IDT72V36110 ⎯ ⎯ ⎯ ⎯ ⎯ 131,072 x 36 • • • • • Higher density, 2Meg and 4Meg SuperSync II FIFOs • • • • • ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 DESCRIPTION: The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 DESCRIPTION (CONTINUED) WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 DESCRIPTION (CONTINUED) operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW- to-HIGH transition ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 PIN DESCRIPTION (TQFP AND PBGA PACKAGES) Symbol Name I/O BM (1) Bus-Matching I BM works with IW and OW to select the bus sizes for both write ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES) Symbol Name I/O SEN SEN enables serial loading of programmable flag offsets. Serial Enable I If Synchronous operation of the write ...
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... Input High Voltage Com’l/Ind’l 2.0 — Input Low Voltage Com’l/Ind’l — — Operating Temperature 0 — Commercial Operating Temperature -40 — Industrial = -40°C to +85°C; JEDEC JESD8-A compliant) A IDT72V36100L IDT72V36110L Commercial and Industrial ( 7-5, 10 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — ...
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... FIFO TM (1) = 3.3V ± 0.15V -40°C to +85°C; JEDEC JESD8-A compliant Commercial Com’l & Ind’l (2) PBGA & TQFP PBGA & TQFP IDT72V36100L6 IDT72V36100L7-5 IDT72V36100L10 IDT72V36110L6 IDT72V36110L7-5 IDT72V36110L10 Min. Max. Min. Max. — 166 — 133 ( — ...
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... JEDEC JESD8-A compliant Commercial IDT72V36100L6 IDT72V36110L6 Min. — 0.6 10 4.5 4.5 8 — — — — 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l IDT72V36100L7-5 IDT72V36110L7-5 Max. Min. Max. Unit 100 — 83 MHz 8 0 — 12 — ns — 5 — ns — ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for t = 10ns CLK Output Load ...
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... PAF to go LOW. Again reads are performed, the PAF will go LOW after (65,537-m) writes for the IDT72V36100 and (131,073-m) writes for the IDT72V36110, where m is the full offset value. The default setting for these values are stated in the footnote of Table 2. ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS IDT72V36100, 72V36110 LD FSEL1 FSEL0 ...
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... FF PAF HF IDT72V36110 ( (n+1) to 65,536 H H 65,537 to (131,072-(m+1 (131,072-m) to 131,071 L L 131,072 IR PAF HF PAE OR IDT72V36110 n (n+2) to 65,537 L H 65,538 to (131,073-(m+1 (131,073-m) to 131,072 H L 131,073 14 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PAE ...
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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V36100 IDT72V36110 Parallel write to registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) ...
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... D/Q19 D/Q17 D/Q8 FULL OFFSET REGISTER (PAF IDT72V36100/IDT72V36110 ⎯ x36 Bus Width 1st Parallel Offset Write/Read Cycle D/Q17 Data Inputs/Outputs D/Q16 EMPTY OFFSET (LSB) REGISTER (PAE ...
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... FULL OFFSET REGISTER (PAF FULL OFFSET REGISTER (PAF) IDT72V36110 ⎯ x9 Bus Width # of Bits Used: 16 bits for the IDT72V36100 17 bits for the IDT72V36110 Note: All unused bits of the LSB & MSB are don’t care APRIL 6, 2006 D/Q0 1 D/Q0 9 D/Q0 17 D/Q0 1 D/Q0 9 ...
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... words should have been written into the FIFO, and read from the FIFO, between Reset (Master or Partial) and the time of Retransmit setup 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 36-bit wide data ( data inputs for 18-bit wide data ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether ...
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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110). See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. ...
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... In FWFT mode reads are performed after reset (MRS or PRS), HF will go LOW after (D-1 writes to the FIFO, where D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes), for the relevant timing information. Because HF is updated by both RCLK and WCLK considered asynchronous ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ASYW, ASYR t RSS FSEL0, FSEL1 t RSS BM, OW ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF 36-BIT FIFO TM t ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 36-BIT FIFO TM 29 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES APRIL 6, 2006 ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 36-BIT FIFO TM 30 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES APRIL 6, 2006 ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...
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... Retransmit setup is complete after OR returns LOW more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110 LOW. ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...
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... There must be at least two words written to the FIFO before a Retransmit operation can be invoked set LOW during MRS. WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V36100 and for the IDT72V36110. Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) 36-BIT FIFO ( ...
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... PAF offset maximum FIFO depth. In IDT Standard mode 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. In FWFT mode 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...
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... NOTES PAF offset maximum FIFO Depth. In IDT Standard Mode 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110. In FWFT Mode 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. 3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition. ...
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... REN NOTES IDT Standard mode maximum FIFO depth 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110 FWFT mode maximum FIFO depth 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110. Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 RCLK REN FFA NOTE LOW and WEN = LOW. Figure 23. Asynchronous Write, ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 Write WCLK 1 WEN SKEW t CYL Last Word W X NOTE LOW and REN = ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 CYC t t CYH CYL Last Word in O/P Register t RPE t EFA EF NOTES ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any ...
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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V36100 can easily be adapted to applications requiring depths greater than 65,536 and 131,072 for the IDT72V36110, with an 36-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. ...
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... TCK t JTCKH Figure 31. Standard JTAG Timing JTAG AC ELECTRICAL CHARACTERISTICS (V = 3.3V CC Parameter JTAG Clock Input Period t IDT72V36100 JTAG Clock HIGH IDT72V36110 JTAG Clock Low Min. Max. Units JTAG Clock Rise Time - 20 ns JTAG Clock Fall Time JTAG Reset ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V36100/72V36110 incorporates the necessary tap controller ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 Input = TMS NOTE: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. Refer to the IEEE Standard Test Access Port ...
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... IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V36100/72V36110, the Part Number field contains the following values: Device Part# Field IDT72V36100 IDT72V36110 31(MSB Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) 0X0 ...
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IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II 65,536 x 36 and 131,072 x 36 HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 7-5ns and 15ns are available as standard device. All other speed grades are available by special order. 2. Green parts are available. For ...