IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 23

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
HALF-FULL FLAG ( HF )
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
If asynchronous PAE configuration is selected, the PAE is asserted LOW
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
TM
36-BIT FIFO
23
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536 for the
IDT72V36100 and 131,072 for the IDT72V36110.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the
IDT72V36100 and 131,073 for the IDT72V36110.
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
for 18-bit wide data or (Q
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
-Q
35
) are data outputs for 36-bit wide data, (Q
0
-Q
n
0
)
-Q
8
) are data outputs for 9-bit wide data.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
0
- Q
17
APRIL 6, 2006
) are data outputs