MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 52

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
For a continuous signal, such as dial tone, where there is no off time, an interrupt occurs when the counter
reaches a maximum count of 508 msec. When a maximum count of 508 msec is reached the P bit can be used
to determine if the interrupt was a result of a transition or a counter overflow. If the P bit remains unchanged
from its previous value then the interrupt is a result of a counter overflow.
Interrupts are generated with a minimum of 4 msec (32 frames) between consecutive IRQs. If a threshold is
crossed within 4 msec of the last interrupt, the interrupt will be held off and the SSCR will be updated after the
4 msec time has transpired. Refer to Fig. 27. For example, if the signal envelope crosses the threshold levels at
point B and point C, then there will be an interrupt generated at point D 32 frames from point A. The SSCR is
updated at the delayed IRQ point D with the last position and count, P=1 and t2, the time between points B to
C.
Table 18 lists the registers which are used for the energy detect blocks.
Refer to MSAN-178 note for Implementing an Algorithm for Interpreting The Measured Cadence of a Call
Progress Signal by the MT90812.
48
EDBLT/EDBHT
EDALT/EDAHT
Low threshold level
High threshold level
SSCR1/2
Register
EDA/B
A, P=1, t0
Interrupt
Figure 27 - Time Between Supervisory Signal Detection Interrupts
Energy Detect
Energy Detect A Low and High Threshold
Energy Detect B Low and High Threshold
Supervisory Signal Cadence Registers
t1
Table 18 - Supervisory Signal Detection Registers
B
4ms
Signal
Envelope
t2
Description
C
D, P=1, t2
interrupt
Delayed
t3
4ms
E, P=0, t3
Interrupt
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4ms
t4
Page
Advance Information
Interrupt
F, P=1, t4
ms