MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 35

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

Advance Information
*X = don’t care
11.1
The receiver transfers incoming data for a specified channel, identified in CM location 70
system read of “D-Channel RX FIFO Output (DRXOUT)” register at 43
FIFO buffer. The following diagram illustrates the data flow for the D-channel data.
The RX control register “D-channel RX FIFO Control Bits (DRXC)” at 41
order, data rate at 1, 2 or 8 bits per frame, Message Length or FIFO Level Interrupt Mode, select start and stop
bits, enable parity, and activate the receiver. Refer to page 66 for more description. The receiver bit order
defines whether the first bit received on the TDM channel is the LSB or MSB read on the microport data bus
(D0 or D7, respectively).
In MLI Mode, when the data is transferred to the RX FIFO the start and stop bits are automatically stripped off.
The start and stop enable (SE) bit in DRXC register is not used and the received message (1 to 256 bits) is
always assumed to be framed by the start and stop bits. The received data is only transferred to the RX FIFO
following the reception of the start bit (the first ‘0’). The status of the parity enable (PE) bit in the DRXC register
* The bit order can be reversed using RXBO and TXBO in DRXC register
Message oriented
Message oriented
Byte oriented with
Byte Oriented
Byte Oriented
with Parity
Byte oriented
Message Oriented
Message Oriented
with Parity
Unframed data
Mode name
with parity
Unframed
FLIM*
FLIM*
FLIM*
MLIM*
MLIM*
Receiver Operation
parity
ST
ST
ST
ST
B7
B7
B7
B6
B6
B6
Interrupt
Mode
MLIM
MLIM
B5
FLIM
FLIM
FLIM
B5
B5
B4
B4
B4
Table 10 - DBRT Modes of Operation
B3
B3
B3
B2
B2
B2
Mode Bit (M)
B1
B1
B1
Figure 21 - DBRT modes
1
1
0
0
0
B0
B0
B0
STP
B7
P
STP
B6
ST
Start-Stop
ST
B5
B7
bits
X
X
0
1
1
B4
B6
B7
B6
B3
B5
H
B5
B2
B4
accesses the next data byte in the RX
H
B1
B4
B3
Parity bit
is used to specify the receiver bit
B0
B3
B2
0
1
0
1
x
STP
B1
P
B2
STP
B1
B0
H
, to the RX FIFO. The
B0
STP
MT90812
bits/frame
bits/frame
bits/frame
bits/frame
bits/frame
P
1, 2, or 8
1, 2, or 8
1, 2, or 8
1, 2, or 8
1, 2, or 8
Bit Rate
STP
31