MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 28

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
8.2
In Constant Delay mode, channel integrity is maintained by making use of a multiple Data Memory buffer
technique. The input channels written in any of the buffers during frame N will be read out during frame N+2.
Table 8 lists the throughput delay for Constant Delay mode for all combinations of source and destination
streams.
Notes: t.s. = time-slot. t.s
Delays are measured in timeslots and at the point in time from when the input channel is completely shifted in and when the output
channel is completely shifted out.
8.3
In a conference the data is read from Data Memory and transferred to the conference block as in constant
delay mode, with a 2 frame delay. If the incoming data is in frame N, then within the first half of frame N+2 the
conference output is calculated and stored in the conference output locations in Data Memory. The conference
output data is then switched to the outgoing data channel in Minimum Delay mode.
The minimum delay possible in a conference is one frame + two 2Mb/s-timeslots = 34 2Mb/s-timeslots. The
maximum delay possible is approximately 2 frames + 1.5 frames + two 2Mb/s-timeslots = 82 2Mb/s-timeslots.
9.0
The MT90812 clock control circuitry selects one of five possible input clock and frame pulse references. The
input clock can be either 4.092, 8.192, or 16.384 MHz as described in Section 9.1, “Input Timing Reference”.
Fig. 16 shows the Clock Control Functional diagram. The clock control circuitry provides an internal master
clock of 8.192 MHz, generates 2.048, 4.096, 8.192, and 10.24 MHz output clocks, F4 and F8 frame pulse
signals, as well as the serial interface timing for STi/o0, STi/o1 and EST0/1 serial streams. These signals are
either generated directly from the input clock source or from an on-chip analog PLL.
The on-chip analog PLL may be used to generate 2.048, 4.096, 8.192, and 10.24 MHz clocks. The PLL
operates in Master and Slave modes. Master mode provides more jitter attenuation while Slave mode
minimizes Phase delay. The PLL can provide the required 4.096 and 10.24 MHz clocks (C4 and C10) to be
supplied to the MT9171/72 DNIC devices. The C4 and C10 clocks meet the requirement that they be frequency
locked and maintain a jitter of less than or equal to 15ns with respect to each other, while maintaining at least
40/60 duty cycle for C10o. Refer to Section 9.3.1, “Master and Slave PLL Modes”.
24
Source and Destination streams
Est0/1 -> Est0/1 2.048 Mb/s
Est0/1 -> Est0/1 4.096 Mb/s
Est0/1 -> Est0/1 8.192 Mb/s
Sti0/1 -> Est0/1 2.048 Mb/s
Sti0/1 -> Est0/1 4.096 Mb/s
Sti0/1 -> Est0/1 8.192 Mb/s
Est0/1 2.048 Mb/s -> Sti0/1
Est0/1 4.096 Mb/s -> Sti0/1
Est0/1 8.192 Mb/s -> Sti0/1
Timing and Clock Control
Constant Delay Mode (CST bit=1)
Delays in Conferencing
Sti0/1 -> Sto0/1
2
. =2Mb/s t.s. = 3.9 us. t.s
Table 8 - Throughput Delay for Constant Delay Mode
Input channel, n,
4
. =4Mb/s t.s.=1.95 us. t.s
range
0-127
0-127
0-31
0-31
0-64
0-31
0-31
0-31
0-31
0-64
Output channel,
8
.=8Mb/s t.s.=0.975 us.
m, range
0-127
0-127
0-31
0-31
0-64
0-31
0-64
0-31
0-31
0-31
Advance Information
Throughput Delay
2x128-(4n-m) t.s
2x128-(n-4m) t.s
2x128-(n-m) t.s
2x64-(2n-m) t.s
2x64-(n-2m) t.s
2x32-(n-m) t.s
2x32-(n-m) t.s
2x64-(n-m) t.s
2x32-(n-m) t.s
2x32-(n-m) t.s
2
2
4
2
2
8
4
4
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8
8
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