MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 38

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
12.1
In either MLI or FLI modes interrupts are generated on TX FIFO empty or 3/4 empty, or end of transmission.
The TX FIFO Interrupt Select (IS) and Interrupt Level (IL) bits in the DTXC register specify the condition for an
interrupt to occur. If the IS bit is set high, then the interrupt occurs when transmission is complete.
If the IS bit is zero, then an interrupt occurs when either the TX FIFO is empty or 3/4 empty depending on the
status of the IL bit. This type of interrupt can be used to continue the message. Therefore, to continue a
message after the TX FIFO empty interrupt occurs, the user can write to the TX FIFO within the number of
frames as shown in Table 12.
The D-Channel TX Enable Interrupt (DTXE) bit in the “Interrupt Enable Register (INTE)” on page 57 enables or
disables the Transmitter interrupts.
13.0 HDLC Resource Allocator Module
The HDLC Resource Allocator (HRA) block in the MT90812 provides an interface to the MT8952 HDLC
Protocol Controller. This interface supports the sharing of the HDLC resource across several MT9171/72 DNIC
devices for communication over the D-Channel. The MSAN-122 application note describes how voice/data
channels and signalling information channels on a digital communications link are supported. Refer to the
MSAN-122 note for a general description of:
The HRA block is described in the following sections.
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Table 12 - Number of available frames to continue the message following TX FIFO empty interrupt
Message oriented with parity
• Connection to MT8952B HDLC Controller
• Connection to MT9171/72 DNIC
• Data Stream Flow
• Generation of TxCEN
• End of the Transmission of a Packet
• TX and RX Handshaking
• Merging of D and C-channels
• Generation of RxCEN
MT8952 HDLC Protocol Controller
MT9171/72 Digital Network Interface Circuit
Shared HDLC Resource Method
General Description of MT90812 and Shared HDLC Configuration
Connection to MT8952 HDLC Controller and MT9171/72 DNIC
TX Control
RX Control
Byte oriented with parity
Transmitter Interrupt Handling
Message oriented
Byte oriented
Mode name
Unframed
Interrupt Mode
MLIM
MLIM
FLIM
FLIM
FLIM
1 bit/frame
10 frames
11 frames
8 frames
8 frames
8 frames
2 bits/frame
4 frames
4 frames
4 frames
5 frames
6 frames
Bit Rate
Advance Information
8 bits/frame
1 frame
1 frame
1 frame
1 frame
1 frame