MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 32

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
9.3.1
The PLL Master/Slave (PMS) bit in the TC register selects the PLL mode. In Master mode the PLL loop filter is
selected to minimize the magnitude of any one clock correction. This preserves the C10o 40/60 duty cycle
given the input jitter as specified on page 95. For example this provides the 10.24 MHz clock required for DNIC
operation with up to 32ns of clock correction on the input clock once per 125us frame. Refer to Intrinsic Jitter
for Master and Slave modes on page 93 and typical Input to Output Jitter Transfer for Master Mode on page 93.
In Slave mode the PLL loop filter is selected to minimize the phase delay on the output clock with respect to the
input clock reference. The typical Input to Output Jitter Transfer for Slave Mode is shown on page 94. In Slave
mode the Loop Filter ensures a phase difference of less than 15 ns. This is assuming an input clock reference
from the Master IDX, where the Master IDX has up to 32 ns of clock correction on the input clock once per 125
us. In an application where the clock reference does not require jitter attenuation the PLL can be used in Slave
mode. For example in a multi-IDX application the Master IDX could have its PLL in Master Mode, and generate
clocks for the other IDX devices. Setting the PLLs of these Slave IDX devices in Slave mode lessens phase
delay while taking advantage of the clock source from the Master IDX. Note: the Master IDX PLL maybe placed
in Slave mode as well if jitter attenuation is not required.
9.4
A watchdog timer monitors C8 input. This requires the presence of a 8.192 MHz clock at C8P_C16. In the
event of the loss of the C8 clock an interrupt is generated and the C8F bit in the Interrupt Status Register
(INTS) is set. The system can service the interrupt and maintain operation of the MT90812 by switching clock
input reference from C8 (CR0-1=01) to C8P (CR0-1=10) and enable the MT90812 to supply C8 output.
This provides redundancy for the clock source in a multiple IDX system. The watchdog timer is enabled by
setting WDE bit in Timing Control Register (TC).The interrupt is enabled by setting C8FE bit in Interrupt Enable
Register (INTE).
28
Watchdog Timer
Master and Slave PLL Modes
Figure 18 - Watchdog Configuration
F4i
C4i
STo0
STi0
STo1
STi1
F4i
C4i
STo0
STi0
STo1
STi1
C8P OSCo
8.192 MHz
C8P OSCo
8.192 MHz
Crystal
IDX A
IDX B
Crystal
EST0
EST1
C10o
EST0
EST1
C10o
C4o
F4o
C4o
F4o
C8
F8
C8
F8
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