MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 40

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
The MT90812 output C2o is a 2.048 MHz clock provided for the MT8952 HDLC controller bit rate clock input.
13.2.2
The DNIC, as mentioned earlier, is used in dual-port mode. The B1 and B2 channels are input/output at DNIC
port DSTi/DSTo in timeslots 0 (B1) and 16 (B2) relative to F0i. The D and C information is input/output at port
CDSTi/CDSTo on channels 0 (D) and 16 (C). The DNICs are 'daisy-chained' together using the delayed frame
pulse output F0o. In dual-port mode the signal F0o comes at the end of channel 0. Supplying it to the next
DNIC in the chain skews its active channels by one channel.
Because two TDM links are used to support these 'daisy-chained' DNICs, up to 16 line circuits may be served
by one HDLC Protocol Controller with this configuration.
13.2.3
Fig. 24 shows five numbered streams which connect a MT90812 to the DNICs and the MT8952 HDLC Protocol
Controller. They are:
1. The STo0 stream from the MT90812 to the DNICs’ DSTi containing B channels.
2. The STo1 stream from the MT90812 to the DNICs’ CDSTi containing D/C-channels.
3. The STi0 stream of the MT90812 from the DNICs’ DSTo containing B channels.
4. The DNICs’ CDSTo containing D/C-channels to the MT90812 STi1 and the MT8952B CDSTi.
5. The MT8952B CDSTo stream to the MT90812 DPER containing formatted D-channel data.
Streams 1 and 3 contain only B channel information. Stream 1 originates from the STo0 of the MT90812 and is
input to DSTi of the DNIC devices. Stream 3 is the opposite direction of stream 1, transferring B-channel
information from DSTo of the DNICs to STi0 of the MT90812.
Streams 2, 4 and 5 are used to pass D- and C-channel information from the microprocessor to the DNICs
through the MT90812 and HDLC protocol controller. D-channel information starting at the microprocessor is
written to the MT8952 transmit buffer. It is formatted and sent out stream 5. Stream 5 connects CDSTo of the
MT8952B to the DPER input of the MT90812.
In the MT90812 the D-channel and C-channel information are merged to form stream 2. The C-channel
information is written by the microprocessor to the Connect Memory of the MT90812. The C-channel
information from Connect Memory is sent out STo1 of the MT90812 along with the D-Channel information from
DPER. Stream 2 connects STo1 from the MT90812 to CDSTi of the DNICs. The merging of the D- and C-
channels is described in Section 13.3.4.
The D- and C-channel information is transferred from the DNICs’ CDSTo on stream 4, to both the MT90812
and the HDLC. The C-channel information is transferred to the Data Memory of the MT90812, where it may be
read directly by the microprocessor. The D-channel information is transferred to the microprocessor through
the MT8952 HDLC Protocol Controller. The MT8952 stores the D-channel information in the 19-byte buffer to
be read by the microprocessor.
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Connection to MT9171/72B DNIC
Data Stream Flow
Advance Information