MT58V512V36D Micron Technology, MT58V512V36D Datasheet - Page 25

• Manufacturer Part Number: MT58V512V36D
• Description: (MT58xxxx) 16Mb SYNCBURST SRAM
• Manufacturer: Micron Technology

register is connected to TDI, and the LSB is connected to
TDO.
IDENTIFICATION (ID) REGISTER
bit code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The
IDCODE is hardwired into the SRAM and can be shifted
out when the TAP controller is in the Shift-DR state. The
ID register has a vendor code and other information
described in the Identification Register Definitions table.
TAP INSTRUCTION SET
OVERVIEW
three-bit instruction register. All combinations are listed
in the Instruction Codes table. Three of these instruc-
tions are listed as RESERVED and should not be used.
The other five instructions are described in detail below.
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST or
the PRELOAD portion of SAMPLE/PRELOAD; rather it
performs a capture of the I/O ring when these instruc-
tions are executed.
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, instruc-
tions are shifted through the instruction register through
the TDI and TDO pins. To execute the instruction once
it is shifted in, the TAP controller needs to be moved into
the Update-IR state.
EXTEST
to be executed whenever the instruction register is loaded
with all 0s. EXTEST is not implemented in this SRAM
TAP controller, and therefore this device is not compli-
ant to 1149.1.
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAMPLE/
PRELOAD instruction has been loaded. There is one
difference between the two instructions. Unlike the
SAMPLE/PRELOAD instruction, EXTEST places the SRAM
outputs in a High-Z state.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
The ID register is loaded with a vendor-specific, 32-
Eight different instructions are possible with the
The TAP controller used in this SRAM is not fully
Instructions are loaded into the TAP controller dur-
EXTEST is a mandatory 1149.1 instruction which is
The TAP controller does recognize an all-0 instruc-
25
PIPELINED, DCD SYNCBURST SRAM
IDCODE
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI and
TDO pins and allows the IDCODE to be shifted out of the
device when the TAP controller enters the Shift-DR
state. The IDCODE instruction is loaded into the in-
struction register upon power-up or whenever the TAP
controller is given a test logic reset state.
SAMPLE Z
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bi-directional pins is captured in the boundary scan
register.
can only operate at a frequency up to 10 MHz, while the
SRAM clock operates more than an order of magnitude
faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but
there is no guarantee as to the value that will be cap-
tured. Repeatable results may not be possible.
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP
controller’s capture setup plus hold time (
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in
the boundary scan register.
data by putting the TAP into the Shift-DR state. This
places the boundary scan register between the TDI and
TDO pins.
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
16Mb: 1 MEG x 18, 512K x 32/36
The IDCODE instruction causes a vendor-specific,
The SAMPLE Z instruction causes the boundary scan
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
When the SAMPLE/PRELOAD instruction is loaded
The user must be aware that the TAP controller clock
To guarantee that the boundary scan register will
Once the data is captured, it is possible to shift out the
Note that since the PRELOAD part of the command
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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