MT58V512V36D Micron Technology, MT58V512V36D Datasheet - Page 17

• Manufacturer Part Number: MT58V512V36D
• Description: (MT58xxxx) 16Mb SYNCBURST SRAM
• Manufacturer: Micron Technology

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Notes 1, 10 unless otherwise noted) (0ºC T
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for +3.3V I/O (V
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
10. If V
2. Measured as HIGH above V
3. This parameter is measured with the output loading shown in Figure 2.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
3 for 2.5V I/O (V
discussion on these parameters.
times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the
required setup and hold times.
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
Voltage tolerances: +3.3V ±0.165 or +2.5V ±0.125V for all values of V
DD
= +3.3V, then V
DD
Q = +2.5V ±0.125V) unless otherwise noted.
DD
Q = +3.3V or +2.5V. If V
IH
and LOW below V
SYMBOL
t
t
t
t
t
t
t
t
KQHZ
t
ADSH
A
KQLZ
OEHZ
t
t
OELZ
ADSS
t
t
KQX
OEQ
t
AAH
t
t
AAS
t
t
t
t
t
CEH
f
t
CES
WH
KH
KQ
WS
AH
DH
KC
KF
KL
AS
DS
+70ºC)
DD
IL
.
MIN
= +2.5V, then V
6.0
2.3
2.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
0
17
PIPELINED, DCD SYNCBURST SRAM
-6
16Mb: 1 MEG x 18, 512K x 32/36
MAX
166
3.5
3.5
3.5
3.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q = +2.5V.
MIN
7.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
DD
0
0
and V
-7.5
MAX
133
DD
4.0
4.2
4.2
4.2
Q.
MIN
3.0
3.0
1.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
DD
10
0
0
Q = +3.3V ±0.165V) and Figure
-10
MAX
100
5.0
5.0
5.0
4.5
©2000, Micron Technology, Inc.
UNITS
MHz
ADVANCE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
3, 4, 5, 6
NOTES
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
8, 9
2
2
3
7