MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 39

• Manufacturer Part Number: MT29F128G08WAAC6
• Description: NAND Flash Memory
• Manufacturer: Micron

Figure 22:
PROGRAM PAGE CACHE MODE 80h-15h
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
RANDOM DATA INPUT
Cache programming is actually a buffered programming mode of the standard PRO-
GRAM PAGE command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by 5 cycles of address, and a full or
partial page of data. The data is initially copied into the cache register, and the CACHE
PROGRAM (15h) command is then latched to the command register. Data is transferred
from the cache register to the data register on the rising edge of WE#. R/B# goes LOW
during this transfer time. After the data has been copied into the data register and R/B#
returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and sub-
sequent programming passes, transfer from the cache register to the data register is held
off until current data register content has been programmed into the array.
The PROGRAM PAGE CACHE MODE command can cross block boundaries. If a PRO-
GRAM PAGE CACHE MODE operation crosses die boundaries, handle as described in
“Interleaved PROGRAM PAGE CACHE MODE Operations” on page 72.
RANDOM DATA INPUT commands are allowed during PROGRAM PAGE CACHE MODE
operations.
Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h,
78h) commands to determine when the cache register is ready to accept new data. The
R/B# pin always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual program-
ming of the array is complete for the current programming cycle.
If just the R/B# pin is used to determine programming completion, the last page of the
program sequence must use the PROGRAM PAGE (10h) command instead of the CACHE
PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every
time, including the last page of the programming sequence, status register bit 5 must be
used to determine when programming is complete (see Figure 23 on page 40).
Bit 1 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-
tion is returned with bit 0 of the status register when bit 5 of the status register is a “1”
(ready state) (see Figure 23 on page 40).
If a RESET (FFh) command is issued during a PROGRAM PAGE CACHE MODE operation
while R/B# or bit 5 or bit 6 of the status register is LOW, the data in the shared memory
cells being programmed could become invalid. Interruption of a PROGRAM operation
on one page could corrupt the data in another page within the block being programmed.
R/B#
I/Ox
80h
Address (5 cycles)
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D
IN
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85h
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Address (2 cycles)
16, 32, 64, 128Gb NAND Flash Memory
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D
IN
10h
Command Definitions
t PROG
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70h
1
Status
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