MT29F128G08WAAC6 Micron, MT29F128G08WAAC6 Datasheet - Page 37
MT29F128G08WAAC6
Manufacturer Part Number
MT29F128G08WAAC6
Description
NAND Flash Memory
Manufacturer
Micron
Datasheet
1.MT29F128G08WAAC6.pdf
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Figure 20:
PDF: 09005aef8278ee3f / Source: 09005aef81f17540
16gb_nand_mlc_l52a__2.fm -Rev. D 5/08 EN
WE#
WE#
R/B#
R/B#
I/Ox
I/Ox
CE#
ALE
RE#
CE#
ALE
RE#
CLE
CLE
PAGE READ CACHE MODE Operation
1
00h
00h
PAGE READ CACHE MODE
Address (5 cycles)
Address (5 cycles)
After this command is issued, R/B# goes LOW (status register bits 6 and 5 = 00) for
t
cate that the cache register is available and that the NAND Flash array is ready. At this
point data can be output from the cache register, beginning at column address 0, by tog-
gling RE#. The RANDOM DATA READ (05h-E0h) command can be used to change the
column address of the data being output by the device.
operation
DCBSYR2. After
Random
30h
31h
Micron Confidential and Proprietary
t
DCBSYR2, R/B# goes HIGH and status register bits 6 and 5 = 11 to indi-
t WB
t DCBSYR2
t R
Data output
37
PAGE READ CACHE MODE
www.DataSheet.net/
Sequential
operation
16, 32, 64, 128Gb NAND Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
31h
t DCBSYR1
3Fh
t DCBSYR2
Data output
Command Definitions
Data output
©2005 Micron Technology, Inc. All rights reserved.
1
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