SCAN18245TSSCX Fairchild Semiconductor, SCAN18245TSSCX Datasheet

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SCAN18245TSSCX

Manufacturer Part Number
SCAN18245TSSCX
Description
IC TRANSCVR 3ST NON-INV 56SSOP
Manufacturer
Fairchild Semiconductor
Series
SCANr
Datasheet

Specifications of SCAN18245TSSCX

Logic Type
Transceiver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
9
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SCAN18245TSSCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
© 2000 Fairchild Semiconductor Corporation
SCAN18245TSSC
SCAN18245T
Non-Inverting Transceiver with 3-STATE Outputs
General Description
The SCAN18245T is a high speed, low-power bidirectional
line driver featuring separate data inputs organized into
dual 9-bit bytes with byte-oriented output enable and direc-
tion control signals. This device is compliant with IEEE
1149.1 Standard Test Access Port and Boundary Scan
Architecture with the incorporation of the defined boundary-
scan test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select (TMS),
and Test Clock (TCK).
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
DS010961
Features
Pin Descriptions
A1
B1
A2
B2
G1, G2
DIR1, DIR2
Pin Names
IEEE 1149.1 (JTAG) Compliant
Dual output enable control signals
3-STATE outputs for bus-oriented applications
9-bit data busses for parity applications
Reduced-swing outputs source 32 mA/sink 64 mA
Guaranteed to drive 50
levels of 0.8V and 2.0V
TTL compatible inputs
25 mil pitch SSOP (Shrink Small Outline Package)
Includes CLAMP and HIGHZ instructions
Member of Fairchild’s SCAN Products
(0–8)
(0–8)
(0–8)
(0–8)
Package Description
Side A1 Inputs or 3-STATE Outputs
Side B1 Inputs or 3-STATE Outputs
Side A2 Inputs or 3-STATE Outputs
Side B2 Inputs or 3-STATE Outputs
Output Enable Pins
Direction of Data Flow Pins
transmission line to TTL input
October 1991
Revised May 2000
Description
www.fairchildsemi.com

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SCAN18245TSSCX Summary of contents

Page 1

... Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Features IEEE 1149.1 (JTAG) Compliant Dual output enable control signals ...

Page 2

Truth Table Inputs A1 (0–8) G1 DIR1 HIGH Voltage Level L LOW Voltage Level Functional Description The SCAN18245 consists of two sets of nine ...

Page 3

Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their loca- tion. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability ...

Page 4

Scan Chain Definition (80 Bits in Length) www.fairchildsemi.com Boundary-Scan Register 4 ...

Page 5

Boundary-Scan Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type 79 DIR1 3 Input TYPE1 Input TYPE1 77 AOE Internal TYPE2 1 76 BOE Internal TYPE2 1 75 DIR2 26 Input TYPE1 ...

Page 6

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Output Diode Current ( 0. 0. Output ...

Page 7

DC Electrical Characteristics Symbol Parameter I Maximum I Per Input CCt CC Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Symbol Parameter ...

Page 8

AC Electrical Characteristics Scan Test Operation Symbol Parameter t , Propagation Delay PLH t TCK to TDO PHL t , Disable Time PLZ t TCK to TDO PHZ t , Enable Time PZL t TCK to TDO PZH t , ...

Page 9

AC Operating Requirements Scan Test Operation Symbol Parameter t Setup Time Data to TCK (Note 11) t Hold Time TCK to Data (Note 11) t Setup Time G1, ...

Page 10

Extended AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH, t Data to Output PHL t , Output Enable Time PZH t PZL t Output Disable Time PHZ, t PLZ t Pin to Pin Skew OSHL (Note 19) HL Data ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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