MT57V1MH18A Micron Semiconductor Products, Inc., MT57V1MH18A Datasheet - Page 2

• Manufacturer Part Number: MT57V1MH18A
• Description: 18Mb DDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

enhance pipelined WRITE cycles and reduce READ-to-
WRITE turnaround time. WRITE cycles are self-timed.
loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.
ing an appropriate reference voltage (V
device is ideally suited for applications requiring very
rapid data transfer by operation in data-doubled
mode. The device is also ideal in applications requiring
the cost benefits of pipelined CMOS SRAMs and the
reduced READ-to-WRITE turnaround times of Late
Write SRAMs.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for cache, network, telecom,
DSP , and other applications that benefit from a very
wide, high-speed data bus.
sramds) for the latest data sheet.
DDR Operation
tion through high-clock frequencies (achieved through
pipelining) and double data rate mode of operation. At
slower frequencies, the DDR SRAM requires a single
18Mb: 2.5V V
MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03
Additional write registers are incorporated to
The device does not utilize internal phase-locked
Four balls are used to implement JTAG test capabili-
The device can be used in HSTL systems by supply-
The SRAM operates from a 2.5V power supply, and
Please refer to Micron’s Web site
The DDR SRAM enables high performance opera-
DD
, HSTL, Pipelined DDRb2 SRAM
(www.micron.com/
REF
2.5V V
). The
2
DD
NO OPERATION (NOP) cycle when transitioning from
a READ to a WRITE cycle. At higher frequencies, a sec-
ond NOP cycle may be required to prevent bus conten-
tion. NOP cycles
a WRITE to a READ.
data for the WRITE are stored in registers. The write
information must be stored because the SRAM cannot
perform the last word write to the array without con-
flicting with the READ. The data stays in this register
until the next WRITE cycle occurs. On the first WRITE
cycle after the READ(s), the stored data from the earlier
WRITE will be written into the SRAM array. This is
called a posted write.
if that address was written in the previous cycle. Dur-
ing this READ cycle, the SRAM array is bypassed, and
data is read instead from the data register storing the
recently written data. This is transparent to the user.
This feature facilitates system data coherency.
cessor, the Claymore DDR SRAM. Single data rate
operation is not supported, hence, no SD/DD# ball is
provided. Only bursts of four are supported. In addi-
tion to the echo clocks, two single-ended input clocks
are available (C and C#). The SRAM synchronizes its
output data to these data clock rising edges if pro-
vided. If not present, C and C# must be tied HIGH and
output timing is derived from K and K#. No differential
clocks are used in this device. This clocking scheme
provides greater system tuning capability than Clay-
more SRAMs and reduces the number of input clocks
required by the bus master.
, HSTL, PIPELINED DDRb2 SRAM
If a READ occurs after a WRITE cycle, address and
A read can be made immediately to an address even
The DDR SRAM differs in some ways from its prede-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
a
re not required when switching from
1 MEG x 18, 512 x 36
©2003 Micron Technology Inc.