MT54V1MH18A Micron Semiconductor Products, Inc., MT54V1MH18A Datasheet - Page 9
MT54V1MH18A
Manufacturer Part Number
MT54V1MH18A
Description
18Mb QDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
Manufacturer
Micron Semiconductor Products, Inc.
Datasheet
1.MT54V1MH18A.pdf
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NOTE:
18Mb: 2.5V V
MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03
1. The address is concatenated with one additional internal LSB to facilitate BURST operation. The address order is
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be simultaneously active.
4. State machine, control timing sequence is controlled by K.
always fixed as: xxx...xxx+0, xxx...xxx+1. Bus cycle is terminated at the end of this sequence (burst count = 2).
WRITE ADDRESS
DD
READ ADDRESS
, HSTL, QDRb2 SRAM
LOAD NEW
LOAD NEW
AT K#↑
always
always
RD
WT
Bus Cycle State Diagram
WRITE DOUBLE
READ DOUBLE
WT
RD
Figure 4:
AT K#↑
9
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
/RD
/WT
DD
1 MEG x 18, 512K x 36
, HSTL, QDRb2 SRAM
WRITE PORT NOP
READ PORT NOP
POWER-UP
R_Init=0
Supply voltage
Supply voltage
provided
provided
©2003 Micron Technology, Inc.
/RD
/WT
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