HY27UF081G2M Hynix Semiconductor, HY27UF081G2M Datasheet - Page 42

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HY27UF081G2M

Manufacturer Part Number
HY27UF081G2M
Description
(HY27UF(08/16)1G2M / HY27SF(08/16)1G2M) 1Gbit (128Mx8bit/64Mx16bit) NAND Flash Memory
Manufacturer
Hynix Semiconductor
Datasheet

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Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
5. APPENDIX : Extra Features
5.1 Automatic Page0 Read after Power Up
The timing diagram related to this operation is shown in Fig. 24
Due to this functionality the CPU can directly download the boot loader from the first page of the NAND flash, storing
it inside the internal cache and starting the execution after the download completed.
5.2 Stacked Devices Access
A small logic inside the devices allows the possibility to stack up to 4 devices in a single package without changing the
pinout of the memory. To do this the internal address register can store up to 29 addresses (512 Mbyte addressing
field) and basing on the 2 MSB pattern each device inside the package can decide if remain active (1 over 4) or “hang-
up” the connection entering the Stand-By.
5.3 Addressing for program operation
Within a block, the pages must be programmed consecutively from LSB (least significant bit) page of the block to MSB
(most significant bit) page of the block. Random address programming is prohibited. See Fig. 28.
Rev 0.6 / Mar. 2005
42

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