MT18LD1672 Micron Semiconductor Products, Inc., MT18LD1672 Datasheet - Page 6

• Manufacturer Part Number: MT18LD1672
• Description: 168-Pin DRAM Dimms, Buffered, (x72), , Status: End of Life (EOL)
• Manufacturer: Micron Semiconductor Products, Inc.

PIN DESCRIPTIONS
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
6, 18, 26, 40, 49, 59, 73,
68, 78, 85, 96, 107, 116,
52-53, 55-58, 60, 65-67,
91-95, 97-101, 103-106,
2-5, 7-11, 13-17, 19-22,
136-137, 139-142, 144,
84, 90, 102, 110, 124,
29, 41-42, 47, 61-64,
1, 12, 23, 32, 43, 54,
69-72, 74-77, 86-89,
33-39, 117-122, 126
111, 113, 115, 125,
133, 143, 157, 168
127, 138, 152, 162
149-151, 153-156,
128, 131, 145-148
PIN NUMBERS
30, 45, 114, 129
28, 46, 112, 130
79-82, 163-166
158-161
83, 167
27, 48
31, 44
132
CAS0#, CAS1#, Buffered Input Column-Address Strobe: CAS# is used to clock in the
CAS4#, CAS5#
RAS0#-RAS3#
WE0#, WE2#
OE0#, OE2#
A0-A12, B0
DQ0-DQ71
SYMBOL
PD1-PD8
ID0, ID1
PDE#
RFU
V
V
DD
SS
Buffered Input Write Enable: WE# is the READ/WRITE control for the DQ
Buffered Input Output Enable: OE# is the input/output control for the
Buffered Input Address Inputs: These inputs are multiplexed and
Buffered
Output
Output
Output
Supply
Supply
Input/
TYPE
Input
Input
–
6
Row-Address Strobe: RAS# is used to clock in the row-
address bits. Two RAS# inputs allow for one x72 bank or
two x36 banks.
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
pins. WE0# controls DQ0-DQ35. WE2# controls DQ36-
DQ71. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE# is
also LOW. If WE goes LOW after CAS# goes LOW, then
the cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form
a READ-MODIFY-WRITE cycle.
DQ pins. OE0# controls DQ0-DQ35. OE2# controls DQ36-
DQ71. These signals may be driven, allowing LATE
WRITE cycles.
clocked by RAS# and CAS#. A0 is common to the DRAMs
used for DQ0-DQ35, while B0 is common to the DRAMs
used for DQ36-DQ71.
Data I/Os: For WRITE cycles, DQ0-DQ71 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ71 act as outputs for the addressed DRAM
location.
Presence-Detect: These pins are read by the host system
and tell the system the DIMM’s personality. They will be
either no connect (1), or they will be driven to V
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V ±0.3V.
Ground.
ID Bits: ID0 = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (V
Presence Detect-Enable: PDE# is the READ control for
the buffered presence-detect pins.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
).
BUFFERED DRAM DIMMs
DESCRIPTION
8, 16, 32 MEG x 72
©2000, Micron Technology, Inc.
OL
(0).