MT18LD1672 Micron Semiconductor Products, Inc., MT18LD1672 Datasheet - Page 2

• Manufacturer Part Number: MT18LD1672
• Description: 168-Pin DRAM Dimms, Buffered, (x72), , Status: End of Life (EOL)
• Manufacturer: Micron Semiconductor Products, Inc.

PART NUMBERS
GENERAL DESCRIPTION
and MT36LD(T)3272(F)X are randomly accessed 64MB,
128MB, and 256MB memories organized in a x72 con-
figuration. They are specially processed to operate from
3V to 3.6V for low-voltage memory systems.
addressed through the address bits. First, the row ad-
dress is latched by the RAS# signal, then the column
address by CAS#. Two copies of address 0 (A0 and B0)
are defined to allow maximum performance for 4-byte
applications which interleave between two 4-byte banks.
A0 is common to the DRAMs used for DQ0-DQ35, while
B0 is common to the DRAMs used for DQ36-DQ71.
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. EARLY WRITE
occurs when WE# goes LOW prior to CAS# going LOW,
and the output pins remain open (High-Z) until the
next CAS# cycle.
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
PART NUMBER
MT9LD872G-x X
MT9LDT872G-x X
MT9LD872FG-x X
MT9LDT872FG-x X
MT18LD1672G-x X
MT18LDT1672G-x X
MT18LD1672FG-x X
MT18LDT1672FG-x X
MT18LDT1672FDG-x X
MT36LD3272G-x X
MT36LDT3272G-x X
MT36LD3272FG-x X
MT36LDT3272FG-x X
MT36LD3272CG-x X
MT36LD3272CFG-x X
x = speed
The Micron
During READ or WRITE cycles, each bit is uniquely
READ and WRITE cycles are selected with the WE#
®
MT9LD(T)872(F)X, MT18LD(T)1672(F)X,
CONFIGURATION
16 Meg x 72 ECC
16 Meg x 72 ECC
16 Meg x 72 ECC
16 Meg x 72 ECC
16 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
32 Meg x 72 ECC
8 Meg x 72 ECC
8 Meg x 72 ECC
8 Meg x 72 ECC
8 Meg x 72 ECC
ADDRESSING
REFRESH
4K
4K
8K
8K
4K
4K
8K
8K
8K
4K
4K
8K
8K
4K
8K
2
EDO PAGE MODE
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back HIGH.
EDO provides for CAS# precharge time (
without the output data going invalid. This elimina-
tion of CAS# output control provides for pipeline READs.
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE# is
pulsed while RAS# and CAS# are LOW, data will toggle
from valid data to High-Z and back to the same valid
data. If OE# is toggled or pulsed after CAS# goes HIGH
while RAS# remains LOW, data will transition to and
remain High-Z.
OR’d, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also tristate the outputs. Indepen-
dent of OE# control, the outputs will disable after
which is referenced from the rising edge of RAS# or
CAS#, whichever occurs last. (Refer to the
MT4LC16M4H9 DRAM data sheet for additional infor-
mation on EDO functionality.)
REFRESH
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and execut-
ing any RAS# cycle (READ, WRITE) or RAS# REFRESH
cycle (RAS#-ONLY, CBR or HIDDEN) so that all 4,096
combinations of RAS# addresses (A0-A11) are executed
at least every 64ms, regardless of sequence. However,
with the RAS#-ONLY REFRESH method some compat-
ibility issues may become apparent (128MB and 256MB
versions only). For example, both 4K and 8K refresh
options require 4,096 CBR REFRESH cycles, yet require
a different number of RAS#-ONLY REFRESH cycles (4K
= 4,096 and 8K = 8,192). JEDEC strongly recommends
the use of CBR REFRESH for these devices. The CBR
REFRESH cycle will invoke the internal refresh counter
for automatic RAS# addressing.
EDO PAGE MODE is an accelerated FAST-PAGE-
FAST-PAGE-MODE modules have traditionally
During an application, if the DQ outputs are wire
Returning RAS# and CAS# HIGH terminates a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BUFFERED DRAM DIMMs
8, 16, 32 MEG x 72
©2000, Micron Technology, Inc.
t
CP) to occur
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OFF,