W90220F Winbond Electronics Corp America, W90220F Datasheet - Page 51

• Manufacturer Part Number: W90220F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Winbond.
51
Bits 0
Bit 1
Bit 2
Bit 3
Bit 4-5 Device mode select
Bit 6-7 Dfifo Read Threshold
DMA mode enable
A low-to-high transition of this bit will make PPI issue a DREQ to DMA controller.
On receiving the corresponding DACK, PPI deasserts the DREQ.
This bit will be cleared by DMA terminal-count (TC) asserting or by a CPU write
cycle with data-in[0] = 0.
Reset Dfifo
Writing a logical one to this bit will assert "Dfifo Reset" for one EXTCLK cycle.
This bit will return to deasserted state automatically after "Dfifo Reset" is issued.
Reset Device
Writing a logical one to this bit will assert "Device Reset" for one EXTCLK cycle.
This bit will return to deasserted state automatically after "Device Reset" is issued.
PWord size
"PWord" defines the basic unit of Dfifo access during CPU cycle.
IER[1] and FCR[4:5] are used to choose device operation mode.
These two bits define the threshold level for triggering data-available interrupt (Irpt_RDA)
of Dfifo during reverse transfering.
0 = PWord is 8 bits (1 byte)
1 = PWord is 32 bits (4 bytes)
{IER[1], FCR[4:5]}
1 x 0
1 x 1
0 0 0
0 0 1
0 1 0
0 1 1
Device Operation Mode
Test Mode
Peripheral Emulation Mode
Standard Mode
PS2 Mode
Fast Standard Mode
ECP Mode
W90220F
Version 0.84