W90220F Winbond Electronics Corp America, W90220F Datasheet - Page 21

• Manufacturer Part Number: W90220F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Winbond.
21
bits
- Polled Mode operation : (refer to "LSR" register discriptions located on Section 5.2.5)
empty.
IIR[4:7] is not affected since no interrupt is enabled.
5.1.6
Overview :
The SSI module within W90220 contains holding registers, shift registers, and other logic to support a variety of
serial data communications protocols and provide a direct connection to external audio/telephony codec devices.
Two 48 halfwords fifos, the transmitter fifo and receiver fifo, have been implented to accelerate both transmittion
and receiving operations. These two fifos can be configured as 48 halfwords or 24 words depth depending on the
data word length.
Block Diagram :
B. Transmitter control :
- No interrupts need be enabled at this mode, the CPU always polls the LSR to check COM port status before
- LSR[7] will be set as long as there is at least one byte in the RX-FIFO, and it is cleared if the RX-FIFO is
- LSR[3:6] will specify error(s) status which is handled the same way as in the interrupt mode operation, the
- LSR[2] will indicate when the TX-FIFO is empty.
- LSR[1] will indicate that both TX-FIFO and shift register are empty.
- LSR[0] will indicate whether there are any errors in the RX-FIFO.
taking any actions.
- Set IER[6] to logic 1 to enable "transmitter empty interrupt" (Irpt_THRE) before transmitter operation.
- Once the transmitter FIFO (TX-FIFO) is empty, the Irpt_THRE is triggered and the corresponding IIR
- The Irpt_THRE is reset after the CPU reads the IIR (IIR[4:7] must be 4'b0010 at that time) or writes a
- Irpt_RDA and Irpt_TOUT has the same interrupt priority (2nd priority) while Irpt_THRE has a lower
are set to inform the CPU to fill the TX-FIFO (maximum 16 bytes of characters).
character into TX-FIFO.
priority (3rd priority).
SYNCHRONOUS SERIAL INTERFACE (SSI)
SDO
Fig 5.1.6-1 SSI Block Diagram
32-bit TX-Shift reg
(48x16/24x32)
TX-FIFO
16/32
16/32
32-bit CPU bus
SYNC
& Shift-in/out
SCLK/SYNC
FIFO Control
control
Logic
SCLK
32-bit RX-Shift reg
(48x16/24x32)
RX-FIFO
16/32
16/32
SDI
W90220F
Version 0.84