W90220F Winbond Electronics Corp America, W90220F Datasheet - Page 19

• Manufacturer Part Number: W90220F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

The above information is the exclusive intellectual property of Winbond Electroncs Corp. and shall not be dsiclosed or distributed or reproduced without permission from
Winbond.
19
Operation Modes :
(Left for Blank)
5.1.5
Overview :
The W90220 contains two Universal Asynchronous Receiver/Transmitter (UART) ports, one of them provides
complete MODEM-control and serial transfermation capabilities, whereas the other one provides only serial
transfermation capability. The UART performs serial-to-parallel conversion on data characters received from a
peripheral device such as MODEM, and parallel-to-serial conversion on data characters received from the CPU.
One 16 bytes transmitter FIFO (TX-FIFO) and one 16 bytes (plus 3 bits of error data per byte) receiver FIFO (RX-
FIFO) have been built in to reduce the number of interrupts presented to the CPU. The CPU can read the complete
status of the UART at any time during the functional operation. Status reported includes error conditions (parity,
overrun, framing, or break interrupt) and states of TX-FIFO and RX-FIFO.
Block Diagram :
- Select (input) :
- nFault (input) :
- ED[0:7] (in/out) : 8-bit bus used to hold data, address or command information in all modes. The bit 0 is the
Compatible Mode : Set high to indicate that the peripheral device is on-line.
ECP Mode
Compatible Mode : Set low by peripheral device to indicate that an error has occured.
ECP Mode
UART
SDO
Fig 5.1.5-1 UART Block Diagram
TX shift register
TX-FIFO (16x8)
& Control
: Used by peripheral to reply to the requested extensibility byte sent by the host during the
: Set high to acknowledge 1284 compatibility during negotiation phase. During ECP mode
negotiation phase.
the peripheral may drive this pin low to request communications with the host. This signal
would be typically used to generate an interrupt to the host. This signal is valid in both
forward and reverse trnasfers.
most significant bit.
8
OSC (14.318Mhz)
Baud Rate
Generator
32-bit CPU bus
RX shift register
RX-FIFO (16x8)
& Control
8
SDI
Modem
Control
Modem
Status
Reg
Reg
8
RTS#
DTR#
OUT1#
OUT2#
CTS#
DSR#
DCD#
RI#
W90220F
Version 0.84