nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 54

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
The nRF24LE1 contains a fast 8-bit MCU, which executes the normal 8051 instruction set.
The architecture eliminates redundant bus states and implements parallel execution of fetch and execution
phases. Most of the one-byte instructions are performed in a single cycle. The MCU uses one clock per
cycle. This leads to a performance improvement rate of 8.0 (in terms of MIPS) with respect to legacy 8051
devices.
The original 8051 had a 12 clock architecture. A machine cycle needed 12 clocks and most instructions
were either one or two machine cycles. Except for MUL and DIV instructions, the 8051 used either 12 or 24
clocks for each instruction. Each cycle in the 8051 also used two memory fetches. In many cases, the sec-
ond fetch was a dummy, and extra clocks were wasted.
Table 12.
the instruction is executed twelve times faster. The average speed advantage is 8.0. However, the real
speed improvement seen in any system depends on the instruction mix.
Revision 1.1
4
MCU
shows the speed advantage compared to a legacy 8051. A speed advantage of 12 implies that
Average: 8.0
advantage
Speed
9.6
4.8
24
12
8
6
4
3
Table 12. Speed advantage summary
instructions
Number of
54 of 191
Sum: 111
27
16
44
18
1
2
1
2
Number of
opcodes
Sum: 255
83
38
89
31
1
2
2
9