nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 132

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

P1.6 p1Di 6
P1.5 p1Di 5
P1.4 p1Di 4
P1.3 p1Di 3
P1.2 p1Di 2
P1.1 p1Di 1
P1.0 p1Di 0
P0.7 p0Di 7
P0.6 p0Di 6
P0.5 p0Di 5
P0.4 p0Di 4
P0.3 p0Di 3
P0.2 p0Di 2
P0.1 p0Di 1
P0.0 p0Di 0
pin
a. Flash SPI interface only activated when PROG is set high, no conflict with runtime operations.
b. Connection depends on configuration register CKLFCTL 2:0
c. Connection depends on configuration register CKLFCTL 2:0
TIMER1
TIMER0
GPINT1
GPINT0
UART/
RXD
Conflict exists, use priorities to determine IO allocation
Conflict may exist depending on device configuration. In the case of a conflict, use priorities to determine IO allocation
CKLFCTL 2:0 = 3'b000: Crystal connected between pin P0.0 and pin P0.1.
CKLFCTL 2:0 = 3'b011: Low-amplitude clock source for ckLF from pin P0.1.
CKLFCTL 2:0 = 3'b100: Digital clock source for ckLF.
CKLFCTL 2: 0 = 3'b000: Crystal connected between pin P0.0 and pin P0.1.
Inputs
connections
nRF24LE1 Preliminary Product Specification
17.3.2
The connection map described in this chapter is valid with the 32-pin 5x5 QFN package. Pins P0.4 to
P1.0 have two system inputs listed per pin. This means that the input from the pin is driving both block
inputs if the pin is configured as an input.
Pins P0.3 - P0.4 are listed with two system outputs, such as p0Do 3 and TXD. In these two cases the Port-
Crossbar combines the two drivers using an AND gate and lets the AND gate drive the pin if it is configured
as an output. The AND gate is chosen since both the TXD and RXD signals are high when idle. The
SMISO pin driver is enabled only when SCSN is active.
Revision 1.1
Default
p1Do 6
p1Do 5
p1Do 4
p1Do 3
p1Do 2
p1Do 1
p1Do 0
p0Do 7
p0Do 6
p0Do 5
p0Do 4
p0Do 3
UART/
TXD
p0Do 2
p0Do 1
p0Do 0
Outputs
Pin assignments in package 32pin 5x5 mm
priority 1
CKLF
CKLF
XOSC32K
b
c
ana
Table 75. Pin out map for the 32 pin 5x5mm package
priority 2
MMISO in
MMOSI out
MSCK
SPI Master
out
Slave/Flash
priority 3
SCSN
FCSN
SMISO out
FMISO
SMOSI in
FMOSI
SSCK
FSCK
132 of 191
Dynamically enabled connections
SPI
a
a
a
a
in
in
out
in
in
in
priority 4
PWM1 out AIN 3
PWM0 out AIN 2
PWM
priority 5
AIN10
AIN 9
AIN 8
AIN 7
AIN 6
AIN 5
AIN 4
AIN1
AIN0
ADC/COMP
ana OCITDI in
ana OCITMS in
ana OCITCK in
ana
ana
ana
ana
ana
ana
ana
ana OCITDO out
priority 6
OCITO
HW Debug
out
priority 7
W2SDA ino
W2SCL ino
2-Wire
ut
ut