nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 161

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
21.3.2
The ADC supports up to 14 external and 2 internal input channels, and can be configured for single ended
or differential measurements. Input channel is selected with the chsel bits. Channel 0 to 13 (AIN0-AIN13)
are external inputs applied through port pins. Channel 14 and 15 are internally generated inputs equal to
1/3 ⋅ VDD and 2/3 ⋅ VDD, respectively. The number of available external inputs depends on package variant.
See
Configure diffm to select between single ended and differential mode. In single ended mode the input
range is from 0V up to the reference voltage V
AIN2 or AIN6 can be used as inverting input in differential mode. Non-inverting input is selected with
chsel . The common-mode voltage must be between 25% and 75% of VDD.
The internally generated 1/3 VDD and 2/3 VDD inputs may be used for supply voltage measurement or cal-
ibration of offset and gain error.
21.3.3
Full-scale range is controlled by the refsel bits. It can be set by an internal bandgap reference (nominally
1.2V), external reference or VDD. The external reference voltage is applied on AIN3 or AIN9, and must be
between 0.8V and 1.5V. It is buffered by an on-chip CMOS buffer with very high input impedance.
21.3.4
The ADC can do 6, 8, 10 or 12 bit conversions. Configure the resol bits to set resolution.
21.3.5
The cont bit selects between single step and continuous conversion mode. In single step mode the ADC
performs one conversion and then stops. In continuous mode it runs continuously with a programmable
sampling rate.
Figure 69.
ADCCON1 register. The busy bit is set to ‘1’ four 16MHz clock cycles afterwards and cleared again when the
conversion result becomes available in the ADCDATH / ADCDATL registers. An interrupt to the MCU
(ADCIRQ) is also generated at the end of conversion.
Revision 1.1
chapter 17 on page 127
illustrates the timing of a single step conversion. The conversion is started by writing to the
Input selection
Reference selection
Resolution
Conversion modes
ADCCON1.busy
ADCCON1
ADCDATA
Figure 69. Timing diagram for single step conversion
for a description of the mapping between port pins and AIN0-AIN13.
t
0
write
T
WUP
REF
Previous value
161 of 191
t
1
, in differential mode from –V
T
Input signal
ACQ
sampled
t
2
T
CONV
t
3
New value
REF
/2 to +V
REF
/2. Either