nRF24LE1 Nordic VLSI, nRF24LE1 Datasheet - Page 154

• Manufacturer Part Number: nRF24LE1
• Manufacturer: Nordic VLSI

nRF24LE1 Preliminary Product Specification
The nRF24LE1 has a single buffered 2-Wire interface. It can be configured to transmit or receive data as
master or slave, at two different baud rates. The 2-Wire is not CBUS compatible.
The 2 wire interface connects to device pins W2SDA and W2SCL.
20.1
20.2
20.2.1
20.2.2
A new transfer is initiated by entering a start condition. This can be done by setting W2CON0.4 to ‘1’, or
simply by writing the first byte to W2DAT. The first byte is always transmitted from the Master.
20.2.2.1
To enter TX mode, MCU must write the address to the Slave it wants the 2-Wire to connect to, or the gen-
eral call address (0x00), to W2DAT. 7:1, and write ‘0’ to the direction bit; W2DAT.0. The byte is then trans-
mitted to the Slave(s). If not masked, an interrupt request is asserted on the rising edge of SCL following
the last bit in the byte. Simultaneously, the acknowledge from the addressed Slave is stored in W2CON1.1.
2-Wire is then ready to accept TX data from the MCU, and the bytewise transmissions will follow the same
procedure as for the first byte.
To do a repeated start, the MCU must set W2CON0.4 before writing a new Slave address and direction bit
to W2DAT. To stop the transfer, it must write ‘1’ to W2CON0.5 after writing the last TX data byte to W2DAT.
Start and stop conditions have lower priorities than pending TX data, that is, W2CON0.4 and W2CON0.5
can be set immediately after the last TX data write. If both bits are set, the stop condition is transmitted
first.
Revision 1.1
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I2C compatible.
Single buffered.
Half-duplex operation.
Supports four modes: Master transmitter, Master receiver, Slave transmitter and Slave receiver.
Supports two baud rates: Standard mode (100 Kbit/s) and Fast mode (400 Kbit/s).
Supports broadcast.
Supports 7-bit addressing.
Supports Slave stall of serial clock (SCL).
The W2CON0.wire2Enable bit must be set to ‘1’ in a separate write operation before any other pro-
If the clockstop feature is used, the W2CON0.clockStop bit should be set to ‘1’ before transmissions
begin. In clockStop mode, all received data must be read from the W2DAT register, even received
addresses. This is necessary to avoid stalling the 2-Wire bus.
Updates to the W2CON1.maskIrq configuration bit should be performed before transmission begins.
Once a ‘1’ has been written to the W2CON0.xStart or W2CON0.xStop bit, the user should not
attempt to cancel the request by clearing the bit at a later time.
gramming of the 2-Wire is attempted.
2-Wire
Features
Functional description
Recommended use
Master transmitter/receiver
TX mode
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