AD9957 Analog Devices, AD9957 Datasheet - Page 35

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
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PRELIMINARY TECHNICAL DATA
CFR2<6> : Data Assembler Holds Last Value bit
CFR2<5> : Sync Sample Error Mask bit
CFR2<3:0> : FM Gain bits .
Control Function Register #3 (CFR3)
CFR3<31:30> : DRV0 (XTAL_OUT) control bits.
CFR3<29:27> : Open . Leave these bits clear.
CFR3<26:24> :
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When CFR2<7>= 0 (default), the Frequency Tuning Word,
Phase Offset and Amplitude Scalar pipe delays are mini-
mized. The output will reflect amplitude changes before it
reflects phase changes, and phase changes before it reflects
frequency changes.
When CFR2<7> = 1, the Frequency Tuning Word, Phase
Offset and Amplitude Scalar pipe delays are implemented
such that the simultaneous application of changes in fre-
quency, phase and amplitude are reflected on the output si-
multaneously too.
When CFR2<6>= 0 (default), the data port drives logic ze-
ros onto the signal processing data path when transmission
is disabled.
When CFR2<6> = 1, the data port holds the last data word
registered when transmission is disabled.
CFR2<5>= 0 disables the SYNC_SMP_ERR pin.
CFR2<5> = 1 (default) enables the SYNC_SMP_ERR pin.
When
modulation is selected via the Data Port Destination bits, if
the Single Tone Data Port Enable bit is set, these bits are
used to select one of 16 possible 16-bit ranges relative to the
32-bit DDS tuning word
These bits set the drive strength of the buffered reference
clock output on pin 93.
As per the table below, these bits set the VCO for the appro-
priate range.
Bits
000
001
010
011
100
101
11x
operating the device in single tone mode and FM
VCO Selection Bits.
00 = OFF (default)
01 = Low drive strength
10 = Mid drive strength
11 = High drive strength
Min
420MHz
485MHz
560MHz
655MHz
830MHz
920MHz
PLL WILL NOT FUNCTION
.
Max
485MHz
560MHz
655MHz
830MHz
920MHz
1000MHz
Rev. PrF | Page 35 of 38
CFR3<21:19> :
CFR3<21:19>
000
001
010
011
100
101
110
111
CFR3<18:16> : OPEN . Leave these bits clear
CFR3<15> :
CFR3<14> : OPEN
CFR3<13:9> : OPEN
CFR3<8> : PLL Enable bit.
CFR3<7:1 >:
When CFR3<15> = 0 The AD9957 REFCLK input divider
is bypassed. The internal sysclk fed to the device (or the
clock multiplier) equals the REFCLK rate
When CFR3<15> = 1 (default) The AD9957 REFCLK input
divider is enabled (to ÷2). The internal sysclk fed to the de-
vice (or the clock multiplier) is equal to ½ the REFCLK rate.
This bit is used strictly for testing, leave SET.
These bits are used for testing; leave CLEAR.
When CFR3<8>= 0 (default). The AD9957 reference clock
rate equals the DAC clock sampling rate. The PLL is by-
passed and the clock multiplier is powered down.
When CFR3<8> = 1, The AD9957 reference clock rate
times the PLL Multiplier bit (integer equivalent) equals the
DAC clock sampling rate.
These bits make up the 8-bit word that is the multiplication
factor used by the PLL Clock Multiplier circuitry. The
decimal equivalent of the binary value of these bits is the
multiplication factor. Only certain values are valid (See Ta-
Table 6 Charge Pump Output Current Settings
As per the table below, these bits set the charge pump
output current.
REFCLK Input Divider Disable bit.
REFCLK Multiplier bits.
Charge Pump Current Bits
Charge Pump Current ( μ A)
200
225
250
275
300
325
350
375
AD9957