AD9957 Analog Devices, AD9957 Datasheet - Page 11

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
4
PRELIMINARY TECHNICAL DATA
SIGNAL PROCESSING (QDUC & BFI MODES)
To better understand the operation of the AD9957 it is helpful
to follow the signal path in quadrature modulation mode from
the parallel data port to the output of the DAC, examining the
function of each block (refer to Figure 4).
All timing within the AD9957 is provided by the internal sys-
tem clock (SYSCLK) signal, which is generated from the timing
source provided to the REFCLK pins.
PDCLK Pin
The timing of input data supplied to the AD9957 is easily facili-
tated with the PDCLK output pin, which serves as a data clock
timing source. In QDUC mode, PDCLK controls the timing of
the 18-bit parallel input port. In BFI mode, PDCLK controls
the timing of the dual serial input port. The PDCLK is provided
as a continuous clock (i.e., always active). However, even
though the PDCLK output is active by default, it can be disabled
via the Enable PDCLK bit in the register map.
In QDUC mode, the AD9957 expects alternating I and Q data
words at the parallel port (see Figure 5). Each rising edge of
PDCLK captures one 16-bit word; that is, two PDCLK cycles
per I/Q pair.. In BFI mode, the AD9957 expects two serial bit
streams each segmented into 16-bit words with each rising edge
of PDCLK indicating a new bit. In either case, the output clock
rate is f
U
.com
PDClk
TxEn
Q In
I In
DATA
as explained in the Input Data Assembler section.
FTW
Programming
Regis ters
3
F
O
R
M
A
T
T
E
R
Serial Data
Timing and
Control
Halfband
Halfband
PW OSF
Filter s
Filter s
Interpolators
(4x)
(4x)
Fixed
2
Q
I
Seria l I/O
IS
QS
Port
Figure 4: Quadrature Modulation Mode -- BlackFin Interface
0
1
1
0
CCI
Inv.
Inv.
CCI
Inte rna l Clock Timing & Control
Programmable
Halfband
Halfband
I Q
Interpolators
RA M
Filter s
Filter s
(4x)
(4x)
IS
QS
Rev. PrF | Page 11 of 38
(1x - 63x)
(1x -63x)
F TW
C I
PW
CCI
C
Control
Po wer
Down
DDS
cos( t+ )
sin( t+ )
TxEnable Pin
The rising edge of the TxENABLE signal is used to synchronize
the device. While TxENABLE is in the Logic 0 state, the device
ignores the data applied to the parallel port allowing the inter-
nal data path to be flushed by forcing zeros down the I and Q
data pathways. On the rising edge of TxENABLE, the device is
ready for the first I word. The first I word is latched into the
device coincident with the rising edge of PDCLK. The next
rising edge of PDCLK latches in a Q word, etc., until
TxENABLE is set to a Logic 0 state by the user.
It is important that the user ensure an even number of PDCLK
intervals are observed during any given TxENABLE period. The
device must capture both an I and a Q sample before the data is
processed along the signal chain.
In BFI mode, operation of the TxENABLE pin is similar except
that instead of the rising edge marking the first "I word", it
marks the first I (and Q) bit in a serial frame.
It is important that the user ensure a multiple of 16 PDCLK
cycles are observed during any given TxENABLE period. The
device must capture a full 16-bit I and Q sample before the data
is processed along the signal chain.
The timing relationship between TxENABLE, PDCLK, and
2
2
Quadrature
Modulator
3
1
0
2
0
1
Inverse Sinc
sin(x)
Gain
DAC
Multiplier
x
Clock
Filter
8
0
1
AUX
DAC
(8-b)
0
1
2
OSF
2
DAC
(14 -b)
AD9957
RefClk
RefClk
DAC
Rs et
Iout
Iout