AD9957 Analog Devices, AD9957 Datasheet - Page 34

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
AD9957
CFR2<23> : Internal IO Update Active bit .
CFR2<22> : Enable IO SYNC CLK bit .
CFR2<21:17> : OPEN . Always leave these bits clear.
CFR2<16> :
CFR2<15:14> : IO Update Rate Control bits .
CFR2<13> : PDCLK Rate Control bit .
4
U
amplitude via the profile registers is not possible.
When CFR2<24> = 1, direct modulation of amplitude
via the profile
chip configurations.
When CFR2<23>= 0 (default), the IO Update feature is
controlled externally through the
is configured as an input..
When CFR2<23> = 1, the IO Update feature is controlled
internally via a down counter. The
configured as an output to signal the user to when IO up-
dates have occurred.
CFR2<22>= 1 (default), activates the IOSYNCCLK pin.
When CFR2<22> = 0, the IOSYNCCLK pin is pulled low.
When CFR2<16> = 0 (default, a serial IO read instruc-
tion reads hex address 07h (FTW register), the serial
port reads back the register at hex address 07h.
When CFR2<16> = 1, a serial IO read instruction reads
hex address 07h (FTW register), the serial port reads
back the active FTW.
These bits are ignored if Internal IO Update is not
activated using bit CFR2<23>
The CFR2<15:14> bits set the clock rate for the IO Up-
date down counter. The table below indicates the clock
rate divisor
When CFR2<13> = 0 (default), the rate out of the
.com
Read Effective FTW bit
CFR2<15:14>
registers is possible, depending upon other
00
01
10
11
I/O_UPDATE
IO SYNC
I/O_UPDATE
Divisor
CLK
1
2
4
8
pin, which
pin, is
Rev. PrF | Page 34 of 38
CFR2<12> : Data Format bit .
CFR2<11> : Enable PDCLK bit
CFR2<10> : PDCLK Invert bit
CFR2<9> : TxEnable Invert bit
CFR2<8> : Q First Data Pairing bit
CFR2<7> : Matched Latency bit .
PDCLK pin is equal to the input data rate.
When CFR2<13> = 1, the rate out of the PDCLK pin is
equal to one half the input data rate. This provides in-
sight into the phase of the signal processing clock, rela-
tive to the input data rate. See the Data Assembler sec-
tion of the functional description for details.
When CFR2<12> = 0 (default), data received is treated as
‘twos complement’ .
When CFR2<12> = 1, data received is treated as ‘offset
binary’ . The MSB of the data word is inverted before be-
ing sent to the signal processing logic.
CFR2<11> = 0 pulls the PDCLK pin low.
CFR2<11>= 1 (default) activates PDCLK pin.
When CFR2<10>= 0 (default), the PDCLK pin is in phase
with the clock that samples the data into the part.
When CFR2<10> = 1, the PDCLK pin is in inverted from
the clock that samples the data into the part.
When CFR2<9>= 0 (default), a logic 1 on the TxEnable pin
indicates I data and a logic 0 on the TxEnable pin indicates
Q data, if the user is employing a continuous timing style on
the TxEnable pin. For burst timing style, if the TxEnable In-
vert bit is cleared, a logic 1 on the TxEnable pin enables the
AD9957 to transmit data and a logic zero indicates no fur-
ther data is to be transmitted.
When CFR2<9> = 1, a logic 1 on the TxEnable pin indi-
cates Q data and a logic 0 on the TxEnable pin indicates I
data, if the user is employing a continuous timing style on
the TxEnable pin. For burst timing style, if the TxEnable In-
vert bit is set, a logic 0 on the TxEnable pin enables the
AD9957 to transmit data and a logic one indicates no fur-
ther data is to be transmitted.
When CFR2<8>= 0 (default), I data precedes Q data in the
assembly of the I/Q data pair that is processing in the
QDUC signal chain.
When CFR2<8> = 1, Q data precedes I data in the assembly
of the I/Q data pair that is processing in the QDUC signal
chain.
PRELIMINARY TECHNICAL DATA