AD9957 Analog Devices, AD9957 Datasheet - Page 17

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
4
PRELIMINARY TECHNICAL DATA
The timing relationship between TxENABLE, PDCLK, and
SINGLE-TONE MODE
A block diagram of the AD9957 operating in the single-tone
mode is shown in Figure 13; grayed out items are inactive. In
this mode, both I and Q data paths are disabled from the 18-bit
parallel data port up to and including the modulator. The in-
ternal DDS core produces a signal whose frequency depends on
the programmed tuning word. The user may select either the
cosine (default) or sine output of the DDS. The sinusoid at the
DDS output can be scaled via a 14-bit amplitude scale factor
(ASF) and optionally routed through the Inverse SINC filter.
Amplitude Scale Factor (ASF)
Output amplitude is controlled by a 14-bit digital multiplier
called the Amplitude Scale Factor (ASF), which is programmed
via the appropriate control registers. It is available for each of
the eight profiles. The LSB weight is 2
TxENABLE
U
D<13:0>
PDCLK
.com
PDClk
I/Q In
TxEn
18
Programming
Parallel Data
Registers
3
Timing &
Control
Q
t
I
DS
t
Q
I
DS
0
1
1
0
Figure 12. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
I
0
t
Inv.
CCI
Inv.
CCI
DH
2
Serial I/O
–14
Port
, which yields a multi-
Halfband
Halfband
Filters
Filters
(4x)
(4x)
Internal Clock Timing & Control
I
1
I Q
AD9957: Single-Tone Mode
(1x - 63x)
(1x -63x)
RAM
CCI
CCI
θ
Figure 13: Single-Tone Mode
G
R
F
F
Rev. PrF | Page 17 of 38
PW
1
0
θ
R
I
FTW
1
0
2
Ramp
Logic
Freq.
Control
Power
Down
θ
ω
DDS
cos(ωt+θ)
sin(ωt+θ)
DATA is shown in Figure 12.
plier range of 0 to 1.99993896484375 (1-2
In addition to the ability to generate single tone signals in this
mode, the AD9957 can also provide 2-, 4-, or 8-level modula-
tion of frequency, phase, or amplitude by means of the eight
available profile registers and the Profile<0:2> pins
I/O_UPDATE Pin
In the single-tone mode, the I/O_UPDATE pin serves as a sig-
nal update strobe. Frequency, phase and amplitude control
words for the DDS are programmed via the serial port (see the
Control Register description). The serial port is an asynchro-
nous interface; the I/O_UPDATE pin allows for synchroniza-
tion of the AD9957 output with external circuitry when new
frequency, phase, or amplitude values are programmed into the
on-chip profile registers. A rising edge initiates transfer of the
2
I
3
2
3
1
0
2
0
1
sin(x)
Gain
DAC
Multiplier
x
Clock
8
0
1
AUX
DAC
(8-b)
0
1
2
I
K – 1
2
DAC
(14-b)
-14
t
DH
).
RefClk
RefClk
DAC
Rset
Iout
Iout
.
AD9957
I
K