AD9957 Analog Devices, AD9957 Datasheet - Page 19

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
4
PRELIMINARY TECHNICAL DATA
REFCLK INPUT
The AD9957 supports a few methods for generating the internal
system clock. An on-chip oscillator circuit is available for initi-
ating a low frequency reference signal by connecting a crystal to
the clock input pins. The system clock may also be generated
using the internal, PLL-based reference clock multiplier, allow-
ing the part to operate with a low frequency clock source while
still providing a high update rate for the DDS and DAC. Using
the clock multiplier can impact the output phase noise charac-
teristics - for best phase noise performance, a clean, stable clock
with a high slew is required. A clock of frequency higher than
the maximum allowable clock rate can be used if the REFCLK
input divide by 2 is enabled using the REFCLK input divider
enable bit CFR3<15>.
REFCLK PLL
Enabling the PLL (via the PLL Enable Bit, CFR3<8>) allows
multiplication of the reference clock frequency. The multiplica-
tion factor in the clock multiplier is set by bits CFR3 <7:1> with
values ranging from 8 to 10 and 12 to 127 (decimal). Pro-
gramming CFR3<7:1> for values less than 8 or 11 is not valid
and will cause unpredictable device performance. The system
clock rate with the clock multiplier enabled is equal to the refer-
ence clock rate times the multiplication factor. When using the
clock multiplier, the correct VCO and charge pump current
XTAL_SEL
Pin (95)
REFCLK: EXTERNAL INTERFACE
The reference clock input circuitry has two modes of operation.
The first mode configures it as an input buffer. In this mode, the
reference clock must be ac-coupled to the input due to internal
dc biasing. This mode supports either differential or single-
ended configurations. If single-ended mode is desired, CLKB
(Pin 91) should be decoupled to AVDD or AGND via a 0.1 μF
capacitor. The next three figures exemplify common reference
clock configurations for the AD9957.
High = 1.8 V logic
High = 1.8 V logic
Low
Low
U
.com
CFR1<7:1> PLL, Bits = M
12 ≤ M ≤ 127, or
8 ≤ M ≤ 10
M < 8, M=11, or
M > 127
12 ≤ M ≤ 127 or
8 ≤ M ≤ 10
M < 8, M=11, or
M > 127
PLL Enabled (CFR3<15>
Yes CFR3<15>=1
No
Yes CFR3<15> = 1
No
Table 5 Clock Mode Options
Rev. PrF | Page 19 of 38
must be selected. The VCO range is selected by programming
the VCO SEL bits, CFR3 <26:24>.. The charge pump current is
programmed through the ICP bits, CFR3<21:19>. See the regis-
ter map for Tables showing the available settings
Whenever the PLL clock multiplier is enabled or the multiplica-
tion value changed, the PLL must reacquire lock. Once lock is
achieved, the LOCK_DETECT signal will be output on pin 19.
While the PLL is out of lock, transmission in the QDUC is
gated off.
REFCLK PLL WITH CRYSTAL
The on-chip oscillator for crystal operation is enabled using
XTAL_SEL (pin 95). The XTAL_SEL pin is an analog input,
operating on 1.8V logic. With the on-chip oscillator enabled,
connecting an external crystal across the REF_CLK and
REF_CLKB inputs produces a low frequency reference clock.
The range of frequencies supported is listed in the specification
table.
A buffer outputs a regenerated REFCLK/crystal oscillator signal
on the XTAL_OUT pin (pin 94). Harmonic interference effects
may be mitigated using DRV slew rate control bits
CFR3<31:30>.
Table 5 summarizes the clock mode options. See the Register
Table/Map section for more detail.
The reference clock inputs can also support an LVPECL or
PECL driver as the reference clock source.
System Clock
(f
REFERENCE
f
f
f
f
SYS CLK
SYS CLK
SYS CLK
SYS CLK
SYS CLK
SOURCE
CLOCK
)
= f
= F
= F
= F
OSC
OSC
REF CLK
REF CLK
× M
× M
Figure 14
BALUN
1:1
Min/Max Freq. Range (MHz)
500 < f
20 < f
500 < f
0 < f
SYS CLK
50 Ω
SYSCLK
0.1 μ F
0.1 μ F
SYSCLK
SYSCLK
< 1000
< 30
< 1000
< 1000
PIN 90
PIN 91
CLK
CLK
AD9957
05252-032