AD9957 Analog Devices, AD9957 Datasheet - Page 15

• Manufacturer Part Number: AD9957
• Description: 1 GSPS Quadrature Digital Upconverter
• Manufacturer: Analog Devices

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DataSheet
4
PRELIMINARY TECHNICAL DATA
The Programmable Interpolator is bypassed when programmed
for an interpolation factor of 1. When bypassed, power to the
stage is removed and the Inverse CCI filter (see above) is also
bypassed, because its compensation is not needed in this case.
The output of the Programmable Interpolator is the data from
the 4× interpolator further upsampled by the CCI filter, ac-
cording to the rate chosen by the user. This results in the input
data being upsampled by a factor of 8× to 252× in steps of 4.
The transfer function of the CCI interpolating filter is
where R is the programmed interpolation factor, and f is the
frequency relative to SYSCLK.
Quadrature Modulator
The digital quadrature modulator stage shifts the frequency of
the base band spectrum of the incoming data stream up to the
desired carrier frequency (this process is known as up-
conversion).
At this point the base band data, which was delivered to the
device at an I/Q sample rate of f
equal to the frequency of SYSCLK, making the data sampling
rate equal to the sampling rate of the carrier signal.
The frequency of the carrier signal is controlled numerically by
a Direct Digital Synthesizer (DDS). The DDS generates the de-
sired carrier frequency from the internal reference clock
(SYSCLK) very precisely. The carrier is applied to the I and Q
multipliers in quadrature fashion (90° phase offset) and
summed, yielding a data stream that represents the quadrature
modulated carrier.
The modulation is done digitally avoiding the phase offset, gain
imbalance and crosstalk issues commonly associated with ana-
log modulators. Note that the modulated “signal” is a number
stream sampled at the rate of SYSCLK, the same rate at which
the DAC is clocked.
The orientation of the modulated signal with respect to the
carrier is controlled by a spectral invert bit. This bit resides in
each of the four profile registers. By default, the time domain
output of the quadrature modulator takes the form:
When the spectral invert bit asserted, it becomes:
DDS Core
The Direct Digital Synthesizer (DDS) block generates the sine
and cosine carrier reference signals that digitally modulate the
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H
I
t I
) (
) (
t
(
f
×
×
)
=
cos
cos
⎛
⎜
⎝
R
k
∑
( )
( )
=
ω
ω
−
1
0
e
t
t
−
−
+
j
2 (
Q
Q
π
fk
) (
) (
)
t
t
⎞
⎟
⎠
5
×
×
sin
sin
( )
( )
IQ
ω
ω
, has been upsampled to a rate
t
t
Rev. PrF | Page 15 of 38
(1)
(2)
(3)
I/Q data. The DDS output is tuned using registers accessed via
the serial programming port. This allows for both precise tun-
ing of the carrier frequency and the ability to change frequency
instantaneously.
The equation relating output frequency (f
digital modulator to the frequency tuning word (FTW) and the
system clock (f
where FTW is a decimal number from 0 to 2,147,483,647
(2
Solving for FTW yields:
The round() function means to round the result to the nearest
integer. For example, for f
MHz, then FTW = 1,433,053,867 (556AAAAB hex).
Inverse SINC Filter
The sampled carrier data stream is the input to the digital-to-
analog converter (DAC) integrated onto the AD9957. The
DAC output spectrum is shaped by the characteristic sin(x)/x
(or SINC) envelope, due to the intrinsic zero-order hold effect
associated with DAC-generated signals. The SINC envelope is
well known and can be compensated for. This envelope restora-
tion function is provided by the Inverse SINC filter that pre-
cedes the DAC. By default, the filter is bypassed. It is enabled
via a bit in the register map. The inverse SINC function is im-
plemented as an FIR filter. It’s response characteristic is the
exact inverse of the SINC response. The Inverse SINC filter pre-
distorts the data prior to its arrival at the DAC. The correction
is only accurate for output frequencies up to approximately 40%
of SYSCLK. NOTE: The inverse SINC filter exhibits ~3.5dB of
insersion loss.
Output Scale Factor (OSF)
Output amplitude is controlled using an 8-bit digital multiplier.
The 8-bit multiplier value is called the Output Scale Factor
(OSF) and is programmed via the appropriate control registers.
It is available for each of the eight profiles. The LSB weight is 2
7
gain extends to nearly a factor of 2 to provide a means to over-
come the intrinsic loss through the modulator when operating
in the quadrature modulation mode. NOTE: Programming the
8-bit multiplier to unity gain (80h) bypasses the stage and reduces
power consumption.
14-Bit DAC
The AD9957 incorporates an integrated 14-bit current-output
DAC. The output current is delivered as a balanced signal using
, which yields a multiplier range of 0 to 1.9921875 (2-2
31
−1).
FTW
f
OUT
=
=
round
⎛
⎜
⎝
FTW
SYSCLK
2
32
⎛
⎜
⎜
⎝
2
32
) is
⎞
⎟
⎠
⎛
⎜ ⎜
⎝
f
SYSCLK
f
SYSCLK
f
OUT
OUT
⎞
⎟ ⎟
⎠
= 41 MHz and f
⎞
⎟
⎟
⎠
OUT
) of the AD9957
SYSCLK
= 122.88
AD9957
-7
). The
(4)
(5)
–