ST92185B STMicroelectronics, ST92185B Datasheet - Page 66

• Manufacturer Part Number: ST92185B
• Description: 16k/24k/32k Rom Hcmos Mcu With On-screen-display
• Manufacturer: STMicroelectronics

ST92185B - TIMING AND CLOCK CONTROLLER
REGISTER DESCRIPTION (Cont’d)
PLL CLOCK CONTROL REGISTER (PXCCR)
R251 - Read/Write
Register Page: 39
Reset value: 0000 0000 (00h)
Bit 7= PXCE. Pixel Clock Enable bit.
0: Pixel and TDSRAM interface clocks are blocked
1: Pixel clock is sent to the display controller and
Bit 6:0= These bits are reserved.
SLICER
(SLCCR)
R252 - Read/ Write
Register Page: 39
Reset value: 0000 0000 (00h)
The HALT mode forces the register to its initializa-
tion state.
66/178
PXCE
TDSRAM interface.
7
7
0
6
0
6
0
CLOCK
5
0
5
0
VMOD
4
0
CONTROL
4
3
0
3
0
2
0
2
0
REGISTER
1
0
1
0
0
0
0
0
Bit 7:5 = These bits are reserved.
Bit 4= VMOD: Video mode selection.
This bit is used to select either 50Hz or 60Hz video
mode. It is set and cleared by software.
0: 50 Hz.
1: 60 Hz.
Bit 3:0= These bits are reserved.
5.2.1 Register Mapping
The Timing Controller has 4 dedicated registers,
mapped in a ST9+ register file page (the page ad-
dress is 39 (27h)), as follows :
FEh
FDh
FCh
FBh
Skew Corrector Control Register
SLicer Clock Control Register
Main Clock Control Register
Pixel Clock Control Register
Page 39 (27h)
SKCCR
PXCCR
SLCCR
MCCR