ST92185B STMicroelectronics, ST92185B Datasheet - Page 145

• Manufacturer Part Number: ST92185B
• Description: 16k/24k/32k Rom Hcmos Mcu With On-screen-display
• Manufacturer: STMicroelectronics

SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.5 Working With Other Protocols
The SPI peripheral offers the following facilities for
operation with S-bus/I
cols:
Note that the I/O bit associated with the SPI should
be returned to a defined state as a normal I/O pin
before changing the SPI protocol.
The following paragraphs provide information on
how to manage these protocols.
7.6.6 I
The I
the two lines being SDA (Serial DAta) and SCL
(Serial CLock). Both are open drain lines, to allow
arbitration. As shown in
with clock low. An I²C bus start condition is the
transition on SDI from 1 to 0 with the SCK held
high. In a stop condition, the SCK is also high and
the transition on SDI is from 0 to 1. During both of
these conditions, if SPEN = 0 and BMS = 1 then
an interrupt request is performed.
Interrupt request on start/stop detection
Hardware clock synchronisation
Arbitration lost flag with an automatic set of data
line
2
C-bus is a two-wire bidirectional data-bus,
2
C-bus Interface
2
C-bus and IM-bus proto-
Figure
5, data is toggled
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
Each transmission consists of nine clock pulses
(SCL line). The first 8 pulses transmit the byte
(MSB first), the ninth pulse is used by the receiver
to acknowledge.
Figure 89. S-Bus / I
Compatibility without S-Bus Chip Select
2
C-bus Peripheral
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