ST92185B STMicroelectronics, ST92185B Datasheet - Page 142

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ST92185B

Manufacturer Part Number
ST92185B
Description
16k/24k/32k Rom Hcmos Mcu With On-screen-display
Manufacturer
STMicroelectronics
Datasheet

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ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
7.6 SERIAL PERIPHERAL INTERFACE (SPI)
7.6.1 Introduction
The Serial Peripheral Interface (SPI) is a general
purpose on-chip shift register peripheral. It allows
communication with external peripherals via an
SPI protocol bus.
In addition, special operating modes allow re-
duced software overhead when implementing I
bus and IM-bus communication standards.
The SPI uses up to 3 pins: Serial Data In (SDI),
Serial Data Out (SDO) and Synchronous Serial
Clock (SCK). Additional I/O pins may act as device
selects or IM-bus address identifier signals.
The main features are:
Figure 86. Block Diagram
n
142/178
Full duplex synchronous transfer if 3 I/O pins are
used
MULTIPLEXER
* Common for Transmit and Receive
ST9 INTERRUPT
INTB0
TRANSMISSION
END OF
SDO
SPEN BMS ARB BUSY CPOL CPHA SPR1 SPR0
SERIAL PERIPHERAL CONTROL REGISTER ( SPICR )
SERIAL PERIPHERAL INTERFACE DATA REGISTER
*
READ BUFFER
( SPIDR )
2
C-
7.6.2 Device-Specific Options
Depending on the ST9 variant and package type,
the SPI interface signals may not be connected to
separate external pins. Refer to the Peripheral
Configuration Chapter for the device pin-out.
Master operation only
4 Programmable bit rates
Programmable clock polarity and phase
Busy Flag
End of transmission interrupt
Additional hardware to facilitate more complex
protocols
R253
SDI SCK/INT2
POLARITY
BAUD RATE
R254
PHASE
INTCLK
DATA BUS
INT2
1
INTERNAL
SERIAL
CLOCK
TO MSPI
CONTROL
LOGIC
VR000347
0

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